From c1843cc66aaa96739142e2d371cab3adfc03d115 Mon Sep 17 00:00:00 2001 From: "djm@kirby.fc.hp.com" Date: Fri, 29 Apr 2005 22:09:13 +0000 Subject: [PATCH] bitkeeper revision 1.1327.1.14 (4272b089iYvr5Anp8Hwey0z6acqlvg) More code cleanup --- .rootkeys | 6 +- xen/arch/ia64/Makefile | 2 +- xen/arch/ia64/ivt.S | 1870 ++++++++++++++++++ xen/arch/ia64/patch/linux-2.6.11/bootmem.h | 17 - xen/arch/ia64/patch/linux-2.6.11/efi.c | 31 +- xen/arch/ia64/patch/linux-2.6.11/entry.S | 189 +- xen/arch/ia64/patch/linux-2.6.11/hpsim_ssc.h | 31 - xen/arch/ia64/patch/linux-2.6.11/irq_ia64.c | 109 +- xen/arch/ia64/patch/linux-2.6.11/ivt.S | 533 ----- xen/arch/ia64/patch/linux-2.6.11/lds.S | 22 - xen/arch/ia64/tools/mkbuildtree | 7 +- xen/arch/ia64/xenirq.c | 77 + 12 files changed, 2073 insertions(+), 821 deletions(-) create mode 100644 xen/arch/ia64/ivt.S delete mode 100644 xen/arch/ia64/patch/linux-2.6.11/bootmem.h delete mode 100644 xen/arch/ia64/patch/linux-2.6.11/hpsim_ssc.h delete mode 100644 xen/arch/ia64/patch/linux-2.6.11/ivt.S delete mode 100644 xen/arch/ia64/patch/linux-2.6.11/lds.S create mode 100644 xen/arch/ia64/xenirq.c diff --git a/.rootkeys b/.rootkeys index 09b55726d2..7895777148 100644 --- a/.rootkeys +++ b/.rootkeys @@ -1078,21 +1078,18 @@ 4239e98a_HX-FCIcXtVqY0BbrDqVug xen/arch/ia64/hypercall.c 421098b3LYAS8xJkQiGP7tiTlyBt0Q xen/arch/ia64/idle0_task.c 421098b3ys5GAr4z6_H1jD33oem82g xen/arch/ia64/irq.c +4272a8e4lavI6DrTvqaIhXeR5RuKBw xen/arch/ia64/ivt.S 421098b3Heh72KuoVlND3CH6c0B0aA xen/arch/ia64/lib/Makefile 421098b3O0MYMUsmYVFy84VV_1gFwQ xen/arch/ia64/mm_init.c -425ae516skiHBZU-Kfwxv2YWXfNRWQ xen/arch/ia64/patch/linux-2.6.11/bootmem.h 425ae516maKAsHBJVSzs19cdRgt3Nw xen/arch/ia64/patch/linux-2.6.11/cpumask.h 425ae516cGqvMzGtihTEsQXAXsuOhQ xen/arch/ia64/patch/linux-2.6.11/efi.c 425ae516Y1A4q4_Kfre3qnDj7lbHJg xen/arch/ia64/patch/linux-2.6.11/entry.S 425ae516txAP-owjzpTJ7ThfzWR8nw xen/arch/ia64/patch/linux-2.6.11/hardirq.h 425ae516PDO1ESDHXHVeDNvlqUfmdQ xen/arch/ia64/patch/linux-2.6.11/head.S -425ae516JR7HWvt1zxJ-wLvEWmJGgg xen/arch/ia64/patch/linux-2.6.11/hpsim_ssc.h 425ae516AHRNmaVuZjJY-9YjmKRDqg xen/arch/ia64/patch/linux-2.6.11/interrupt.h 425ae516U2wFUzrUJQUpy3z38jZHsQ xen/arch/ia64/patch/linux-2.6.11/io.h 425ae516GGRmXijPBLC5ii6yWOn0rg xen/arch/ia64/patch/linux-2.6.11/irq_ia64.c -425ae516qQA5dHuIybqfN3nEzM_Zvg xen/arch/ia64/patch/linux-2.6.11/ivt.S 425ae516atiECmpn_6nZDw4kkmbJ6g xen/arch/ia64/patch/linux-2.6.11/kregs.h -425ae516lwlYwHG1Jv93kC3tfU5caw xen/arch/ia64/patch/linux-2.6.11/lds.S 425ae516Je2zI-Iw30_uGhvUYdlCZQ xen/arch/ia64/patch/linux-2.6.11/mca_asm.h 425ae5160-9wHxh0tOnIjavEjt6W0A xen/arch/ia64/patch/linux-2.6.11/minstate.h 425ae516N7SaORdbodDr90tmtCzYXw xen/arch/ia64/patch/linux-2.6.11/mm_contig.c @@ -1168,6 +1165,7 @@ 41a26ebc--sjlYZQxmIxyCx3jw70qA xen/arch/ia64/vcpu.c 421098b6M2WhsJ_ZMzFamAQcdc5gzw xen/arch/ia64/vhpt.c 41a26ebc4jSBGQOuyNIPDST58mNbBw xen/arch/ia64/xenasm.S +4272adaeit9raZ9KnjO_wR4Ii9LJNQ xen/arch/ia64/xenirq.c 427162263zDUiPmTj-lP4eGyXs5eIg xen/arch/ia64/xenmem.c 421098b6mWyFPtkhPz9h1LCmKpoCLg xen/arch/ia64/xenmisc.c 421098b6lY2JzrV1oFDbrt7XQhtElg xen/arch/ia64/xensetup.c diff --git a/xen/arch/ia64/Makefile b/xen/arch/ia64/Makefile index cde36319dc..85d817079a 100644 --- a/xen/arch/ia64/Makefile +++ b/xen/arch/ia64/Makefile @@ -7,7 +7,7 @@ OBJS = xensetup.o setup.o time.o irq.o ia64_ksyms.o process.o smp.o \ machvec.o dom0_ops.o domain.o \ idle0_task.o pal.o hpsim.o efi.o efi_stub.o ivt.o mm_contig.o \ xenmem.o sal.o cmdline.o mm_init.o tlb.o smpboot.o \ - extable.o linuxextable.o \ + extable.o linuxextable.o xenirq.o \ regionreg.o entry.o unaligned.o privop.o vcpu.o \ irq_ia64.o irq_lsapic.o vhpt.o xenasm.o dom_fw.o # perfmon.o diff --git a/xen/arch/ia64/ivt.S b/xen/arch/ia64/ivt.S new file mode 100644 index 0000000000..f68e78a834 --- /dev/null +++ b/xen/arch/ia64/ivt.S @@ -0,0 +1,1870 @@ + +#ifdef XEN +//#define CONFIG_DISABLE_VHPT // FIXME: change when VHPT is enabled?? +// these are all hacked out for now as the entire IVT +// will eventually be replaced... just want to use it +// for startup code to handle TLB misses +//#define ia64_leave_kernel 0 +//#define ia64_ret_from_syscall 0 +//#define ia64_handle_irq 0 +//#define ia64_fault 0 +#define ia64_illegal_op_fault 0 +#define ia64_prepare_handle_unaligned 0 +#define ia64_bad_break 0 +#define ia64_trace_syscall 0 +#define sys_call_table 0 +#define sys_ni_syscall 0 +#include +#endif +/* + * arch/ia64/kernel/ivt.S + * + * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co + * Stephane Eranian + * David Mosberger + * Copyright (C) 2000, 2002-2003 Intel Co + * Asit Mallick + * Suresh Siddha + * Kenneth Chen + * Fenghua Yu + * + * 00/08/23 Asit Mallick TLB handling for SMP + * 00/12/20 David Mosberger-Tang DTLB/ITLB handler now uses virtual PT. + */ +/* + * This file defines the interruption vector table used by the CPU. + * It does not include one entry per possible cause of interruption. + * + * The first 20 entries of the table contain 64 bundles each while the + * remaining 48 entries contain only 16 bundles each. + * + * The 64 bundles are used to allow inlining the whole handler for critical + * interruptions like TLB misses. + * + * For each entry, the comment is as follows: + * + * // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51) + * entry offset ----/ / / / / + * entry number ---------/ / / / + * size of the entry -------------/ / / + * vector name -------------------------------------/ / + * interruptions triggering this vector ----------------------/ + * + * The table is 32KB in size and must be aligned on 32KB boundary. + * (The CPU ignores the 15 lower bits of the address) + * + * Table is based upon EAS2.6 (Oct 1999) + */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if 1 +# define PSR_DEFAULT_BITS psr.ac +#else +# define PSR_DEFAULT_BITS 0 +#endif + +#if 0 + /* + * This lets you track the last eight faults that occurred on the CPU. Make sure ar.k2 isn't + * needed for something else before enabling this... + */ +# define DBG_FAULT(i) mov r16=ar.k2;; shl r16=r16,8;; add r16=(i),r16;;mov ar.k2=r16 +#else +# define DBG_FAULT(i) +#endif + +#define MINSTATE_VIRT /* needed by minstate.h */ +#include "minstate.h" + +#define FAULT(n) \ + mov r31=pr; \ + mov r19=n;; /* prepare to save predicates */ \ + br.sptk.many dispatch_to_fault_handler + +#ifdef XEN +#define REFLECT(n) \ + mov r31=pr; \ + mov r19=n;; /* prepare to save predicates */ \ + br.sptk.many dispatch_reflection +#endif + + .section .text.ivt,"ax" + + .align 32768 // align on 32KB boundary + .global ia64_ivt +ia64_ivt: +///////////////////////////////////////////////////////////////////////////////////////// +// 0x0000 Entry 0 (size 64 bundles) VHPT Translation (8,20,47) +ENTRY(vhpt_miss) + DBG_FAULT(0) + /* + * The VHPT vector is invoked when the TLB entry for the virtual page table + * is missing. This happens only as a result of a previous + * (the "original") TLB miss, which may either be caused by an instruction + * fetch or a data access (or non-access). + * + * What we do here is normal TLB miss handing for the _original_ miss, followed + * by inserting the TLB entry for the virtual page table page that the VHPT + * walker was attempting to access. The latter gets inserted as long + * as both L1 and L2 have valid mappings for the faulting address. + * The TLB entry for the original miss gets inserted only if + * the L3 entry indicates that the page is present. + * + * do_page_fault gets invoked in the following cases: + * - the faulting virtual address uses unimplemented address bits + * - the faulting virtual address has no L1, L2, or L3 mapping + */ + mov r16=cr.ifa // get address that caused the TLB miss +#ifdef CONFIG_HUGETLB_PAGE + movl r18=PAGE_SHIFT + mov r25=cr.itir +#endif + ;; + rsm psr.dt // use physical addressing for data + mov r31=pr // save the predicate registers + mov r19=IA64_KR(PT_BASE) // get page table base address + shl r21=r16,3 // shift bit 60 into sign bit + shr.u r17=r16,61 // get the region number into r17 + ;; + shr r22=r21,3 +#ifdef CONFIG_HUGETLB_PAGE + extr.u r26=r25,2,6 + ;; + cmp.ne p8,p0=r18,r26 + sub r27=r26,r18 + ;; +(p8) dep r25=r18,r25,2,6 +(p8) shr r22=r22,r27 +#endif + ;; + cmp.eq p6,p7=5,r17 // is IFA pointing into to region 5? + shr.u r18=r22,PGDIR_SHIFT // get bits 33-63 of the faulting address + ;; +(p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place + + srlz.d + LOAD_PHYSICAL(p6, r19, swapper_pg_dir) // region 5 is rooted at swapper_pg_dir + + .pred.rel "mutex", p6, p7 +(p6) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT +(p7) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3 + ;; +(p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=PTA + IFA(33,42)*8 +(p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=PTA + (((IFA(61,63) << 7) | IFA(33,39))*8) + cmp.eq p7,p6=0,r21 // unused address bits all zeroes? + shr.u r18=r22,PMD_SHIFT // shift L2 index into position + ;; + ld8 r17=[r17] // fetch the L1 entry (may be 0) + ;; +(p7) cmp.eq p6,p7=r17,r0 // was L1 entry NULL? + dep r17=r18,r17,3,(PAGE_SHIFT-3) // compute address of L2 page table entry + ;; +(p7) ld8 r20=[r17] // fetch the L2 entry (may be 0) + shr.u r19=r22,PAGE_SHIFT // shift L3 index into position + ;; +(p7) cmp.eq.or.andcm p6,p7=r20,r0 // was L2 entry NULL? + dep r21=r19,r20,3,(PAGE_SHIFT-3) // compute address of L3 page table entry + ;; +(p7) ld8 r18=[r21] // read the L3 PTE + mov r19=cr.isr // cr.isr bit 0 tells us if this is an insn miss + ;; +(p7) tbit.z p6,p7=r18,_PAGE_P_BIT // page present bit cleared? + mov r22=cr.iha // get the VHPT address that caused the TLB miss + ;; // avoid RAW on p7 +(p7) tbit.nz.unc p10,p11=r19,32 // is it an instruction TLB miss? + dep r23=0,r20,0,PAGE_SHIFT // clear low bits to get page address + ;; +(p10) itc.i r18 // insert the instruction TLB entry +(p11) itc.d r18 // insert the data TLB entry +(p6) br.cond.spnt.many page_fault // handle bad address/page not present (page fault) + mov cr.ifa=r22 + +#ifdef CONFIG_HUGETLB_PAGE +(p8) mov cr.itir=r25 // change to default page-size for VHPT +#endif + + /* + * Now compute and insert the TLB entry for the virtual page table. We never + * execute in a page table page so there is no need to set the exception deferral + * bit. + */ + adds r24=__DIRTY_BITS_NO_ED|_PAGE_PL_0|_PAGE_AR_RW,r23 + ;; +(p7) itc.d r24 + ;; +#ifdef CONFIG_SMP + /* + * Tell the assemblers dependency-violation checker that the above "itc" instructions + * cannot possibly affect the following loads: + */ + dv_serialize_data + + /* + * Re-check L2 and L3 pagetable. If they changed, we may have received a ptc.g + * between reading the pagetable and the "itc". If so, flush the entry we + * inserted and retry. + */ + ld8 r25=[r21] // read L3 PTE again + ld8 r26=[r17] // read L2 entry again + ;; + cmp.ne p6,p7=r26,r20 // did L2 entry change + mov r27=PAGE_SHIFT<<2 + ;; +(p6) ptc.l r22,r27 // purge PTE page translation +(p7) cmp.ne.or.andcm p6,p7=r25,r18 // did L3 PTE change + ;; +(p6) ptc.l r16,r27 // purge translation +#endif + + mov pr=r31,-1 // restore predicate registers + rfi +END(vhpt_miss) + + .org ia64_ivt+0x400 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x0400 Entry 1 (size 64 bundles) ITLB (21) +ENTRY(itlb_miss) + DBG_FAULT(1) +#ifdef XEN + VHPT_CCHAIN_LOOKUP(itlb_miss,i) +#ifdef VHPT_GLOBAL + br.cond.sptk page_fault + ;; +#endif +#endif + /* + * The ITLB handler accesses the L3 PTE via the virtually mapped linear + * page table. If a nested TLB miss occurs, we switch into physical + * mode, walk the page table, and then re-execute the L3 PTE read + * and go on normally after that. + */ + mov r16=cr.ifa // get virtual address + mov r29=b0 // save b0 + mov r31=pr // save predicates +.itlb_fault: + mov r17=cr.iha // get virtual address of L3 PTE + movl r30=1f // load nested fault continuation point + ;; +1: ld8 r18=[r17] // read L3 PTE + ;; + mov b0=r29 + tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared? +(p6) br.cond.spnt page_fault + ;; + itc.i r18 + ;; +#ifdef CONFIG_SMP + /* + * Tell the assemblers dependency-violation checker that the above "itc" instructions + * cannot possibly affect the following loads: + */ + dv_serialize_data + + ld8 r19=[r17] // read L3 PTE again and see if same + mov r20=PAGE_SHIFT<<2 // setup page size for purge + ;; + cmp.ne p7,p0=r18,r19 + ;; +(p7) ptc.l r16,r20 +#endif + mov pr=r31,-1 + rfi +END(itlb_miss) + + .org ia64_ivt+0x0800 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x0800 Entry 2 (size 64 bundles) DTLB (9,48) +ENTRY(dtlb_miss) + DBG_FAULT(2) +#ifdef XEN + VHPT_CCHAIN_LOOKUP(dtlb_miss,d) +#ifdef VHPT_GLOBAL + br.cond.sptk page_fault + ;; +#endif +#endif + /* + * The DTLB handler accesses the L3 PTE via the virtually mapped linear + * page table. If a nested TLB miss occurs, we switch into physical + * mode, walk the page table, and then re-execute the L3 PTE read + * and go on normally after that. + */ + mov r16=cr.ifa // get virtual address + mov r29=b0 // save b0 + mov r31=pr // save predicates +dtlb_fault: + mov r17=cr.iha // get virtual address of L3 PTE + movl r30=1f // load nested fault continuation point + ;; +1: ld8 r18=[r17] // read L3 PTE + ;; + mov b0=r29 + tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared? +(p6) br.cond.spnt page_fault + ;; + itc.d r18 + ;; +#ifdef CONFIG_SMP + /* + * Tell the assemblers dependency-violation checker that the above "itc" instructions + * cannot possibly affect the following loads: + */ + dv_serialize_data + + ld8 r19=[r17] // read L3 PTE again and see if same + mov r20=PAGE_SHIFT<<2 // setup page size for purge + ;; + cmp.ne p7,p0=r18,r19 + ;; +(p7) ptc.l r16,r20 +#endif + mov pr=r31,-1 + rfi +END(dtlb_miss) + + .org ia64_ivt+0x0c00 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x0c00 Entry 3 (size 64 bundles) Alt ITLB (19) +ENTRY(alt_itlb_miss) + DBG_FAULT(3) +#ifdef XEN +//#ifdef VHPT_GLOBAL +// VHPT_CCHAIN_LOOKUP(alt_itlb_miss,i) +// br.cond.sptk page_fault +// ;; +//#endif +#endif + mov r16=cr.ifa // get address that caused the TLB miss + movl r17=PAGE_KERNEL + mov r21=cr.ipsr + movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff) + mov r31=pr + ;; +#ifdef CONFIG_DISABLE_VHPT + shr.u r22=r16,61 // get the region number into r21 + ;; + cmp.gt p8,p0=6,r22 // user mode + ;; +(p8) thash r17=r16 + ;; +(p8) mov cr.iha=r17 +(p8) mov r29=b0 // save b0 +(p8) br.cond.dptk .itlb_fault +#endif + extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl + and r19=r19,r16 // clear ed, reserved bits, and PTE control bits + shr.u r18=r16,57 // move address bit 61 to bit 4 + ;; + andcm r18=0x10,r18 // bit 4=~address-bit(61) + cmp.ne p8,p0=r0,r23 // psr.cpl != 0? + or r19=r17,r19 // insert PTE control bits into r19 + ;; + or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6 +(p8) br.cond.spnt page_fault + ;; + itc.i r19 // insert the TLB entry + mov pr=r31,-1 + rfi +END(alt_itlb_miss) + + .org ia64_ivt+0x1000 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x1000 Entry 4 (size 64 bundles) Alt DTLB (7,46) +ENTRY(alt_dtlb_miss) + DBG_FAULT(4) +#ifdef XEN +//#ifdef VHPT_GLOBAL +// VHPT_CCHAIN_LOOKUP(alt_dtlb_miss,d) +// br.cond.sptk page_fault +// ;; +//#endif +#endif + mov r16=cr.ifa // get address that caused the TLB miss + movl r17=PAGE_KERNEL + mov r20=cr.isr + movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff) + mov r21=cr.ipsr + mov r31=pr + ;; +#ifdef CONFIG_DISABLE_VHPT + shr.u r22=r16,61 // get the region number into r21 + ;; + cmp.gt p8,p0=6,r22 // access to region 0-5 + ;; +(p8) thash r17=r16 + ;; +(p8) mov cr.iha=r17 +(p8) mov r29=b0 // save b0 +(p8) br.cond.dptk dtlb_fault +#endif + extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl + and r22=IA64_ISR_CODE_MASK,r20 // get the isr.code field + tbit.nz p6,p7=r20,IA64_ISR_SP_BIT // is speculation bit on? + shr.u r18=r16,57 // move address bit 61 to bit 4 + and r19=r19,r16 // clear ed, reserved bits, and PTE control bits + tbit.nz p9,p0=r20,IA64_ISR_NA_BIT // is non-access bit on? + ;; + andcm r18=0x10,r18 // bit 4=~address-bit(61) + cmp.ne p8,p0=r0,r23 +(p9) cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22 // check isr.code field +(p8) br.cond.spnt page_fault +#ifdef XEN + ;; + // FIXME: inadequate test, this is where we test for Xen address + // note that 0xf000 (cached) and 0xd000 (uncached) addresses + // should be OK. (Though no I/O is done in Xen, EFI needs uncached + // addresses and some domain EFI calls are passed through) + tbit.nz p0,p8=r16,60 +(p8) br.cond.spnt page_fault +//(p8) br.cond.spnt 0 + ;; +#endif + + dep r21=-1,r21,IA64_PSR_ED_BIT,1 + or r19=r19,r17 // insert PTE control bits into r19 + ;; + or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6 +(p6) mov cr.ipsr=r21 + ;; +(p7) itc.d r19 // insert the TLB entry + mov pr=r31,-1 + rfi +END(alt_dtlb_miss) + + .org ia64_ivt+0x1400 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x1400 Entry 5 (size 64 bundles) Data nested TLB (6,45) +ENTRY(nested_dtlb_miss) + /* + * In the absence of kernel bugs, we get here when the virtually mapped linear + * page table is accessed non-speculatively (e.g., in the Dirty-bit, Instruction + * Access-bit, or Data Access-bit faults). If the DTLB entry for the virtual page + * table is missing, a nested TLB miss fault is triggered and control is + * transferred to this point. When this happens, we lookup the pte for the + * faulting address by walking the page table in physical mode and return to the + * continuation point passed in register r30 (or call page_fault if the address is + * not mapped). + * + * Input: r16: faulting address + * r29: saved b0 + * r30: continuation address + * r31: saved pr + * + * Output: r17: physical address of L3 PTE of faulting address + * r29: saved b0 + * r30: continuation address + * r31: saved pr + * + * Clobbered: b0, r18, r19, r21, psr.dt (cleared) + */ + rsm psr.dt // switch to using physical data addressing + mov r19=IA64_KR(PT_BASE) // get the page table base address + shl r21=r16,3 // shift bit 60 into sign bit + ;; + shr.u r17=r16,61 // get the region number into r17 + ;; + cmp.eq p6,p7=5,r17 // is faulting address in region 5? + shr.u r18=r16,PGDIR_SHIFT // get bits 33-63 of faulting address + ;; +(p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place + + srlz.d + LOAD_PHYSICAL(p6, r19, swapper_pg_dir) // region 5 is rooted at swapper_pg_dir + + .pred.rel "mutex", p6, p7 +(p6) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT +(p7) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3 + ;; +(p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=PTA + IFA(33,42)*8 +(p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=PTA + (((IFA(61,63) << 7) | IFA(33,39))*8) + cmp.eq p7,p6=0,r21 // unused address bits all zeroes? + shr.u r18=r16,PMD_SHIFT // shift L2 index into position + ;; + ld8 r17=[r17] // fetch the L1 entry (may be 0) + ;; +(p7) cmp.eq p6,p7=r17,r0 // was L1 entry NULL? + dep r17=r18,r17,3,(PAGE_SHIFT-3) // compute address of L2 page table entry + ;; +(p7) ld8 r17=[r17] // fetch the L2 entry (may be 0) + shr.u r19=r16,PAGE_SHIFT // shift L3 index into position + ;; +(p7) cmp.eq.or.andcm p6,p7=r17,r0 // was L2 entry NULL? + dep r17=r19,r17,3,(PAGE_SHIFT-3) // compute address of L3 page table entry +(p6) br.cond.spnt page_fault + mov b0=r30 + br.sptk.many b0 // return to continuation point +END(nested_dtlb_miss) + + .org ia64_ivt+0x1800 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x1800 Entry 6 (size 64 bundles) Instruction Key Miss (24) +ENTRY(ikey_miss) +#ifdef XEN + REFLECT(6) +#endif + DBG_FAULT(6) + FAULT(6) +END(ikey_miss) + + //----------------------------------------------------------------------------------- + // call do_page_fault (predicates are in r31, psr.dt may be off, r16 is faulting address) +ENTRY(page_fault) + ssm psr.dt + ;; + srlz.i + ;; + SAVE_MIN_WITH_COVER +#ifdef XEN + alloc r15=ar.pfs,0,0,4,0 + mov out0=cr.ifa + mov out1=cr.isr + mov out3=cr.itir +#else + alloc r15=ar.pfs,0,0,3,0 + mov out0=cr.ifa + mov out1=cr.isr +#endif + adds r3=8,r2 // set up second base pointer + ;; + ssm psr.ic | PSR_DEFAULT_BITS + ;; + srlz.i // guarantee that interruption collectin is on + ;; +(p15) ssm psr.i // restore psr.i + movl r14=ia64_leave_kernel + ;; + SAVE_REST + mov rp=r14 + ;; + adds out2=16,r12 // out2 = pointer to pt_regs + br.call.sptk.many b6=ia64_do_page_fault // ignore return address +END(page_fault) + + .org ia64_ivt+0x1c00 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51) +ENTRY(dkey_miss) +#ifdef XEN + REFLECT(7) +#endif + DBG_FAULT(7) + FAULT(7) +END(dkey_miss) + + .org ia64_ivt+0x2000 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x2000 Entry 8 (size 64 bundles) Dirty-bit (54) +ENTRY(dirty_bit) +#ifdef XEN + REFLECT(8) +#endif + DBG_FAULT(8) + /* + * What we do here is to simply turn on the dirty bit in the PTE. We need to + * update both the page-table and the TLB entry. To efficiently access the PTE, + * we address it through the virtual page table. Most likely, the TLB entry for + * the relevant virtual page table page is still present in the TLB so we can + * normally do this without additional TLB misses. In case the necessary virtual + * page table TLB entry isn't present, we take a nested TLB miss hit where we look + * up the physical address of the L3 PTE and then continue at label 1 below. + */ + mov r16=cr.ifa // get the address that caused the fault + movl r30=1f // load continuation point in case of nested fault + ;; + thash r17=r16 // compute virtual address of L3 PTE + mov r29=b0 // save b0 in case of nested fault + mov r31=pr // save pr +#ifdef CONFIG_SMP + mov r28=ar.ccv // save ar.ccv + ;; +1: ld8 r18=[r17] + ;; // avoid RAW on r18 + mov ar.ccv=r18 // set compare value for cmpxchg + or r25=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits + ;; + cmpxchg8.acq r26=[r17],r25,ar.ccv + mov r24=PAGE_SHIFT<<2 + ;; + cmp.eq p6,p7=r26,r18 + ;; +(p6) itc.d r25 // install updated PTE + ;; + /* + * Tell the assemblers dependency-violation checker that the above "itc" instructions + * cannot possibly affect the following loads: + */ + dv_serialize_data + + ld8 r18=[r17] // read PTE again + ;; + cmp.eq p6,p7=r18,r25 // is it same as the newly installed + ;; +(p7) ptc.l r16,r24 + mov b0=r29 // restore b0 + mov ar.ccv=r28 +#else + ;; +1: ld8 r18=[r17] + ;; // avoid RAW on r18 + or r18=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits + mov b0=r29 // restore b0 + ;; + st8 [r17]=r18 // store back updated PTE + itc.d r18 // install updated PTE +#endif + mov pr=r31,-1 // restore pr + rfi +END(dirty_bit) + + .org ia64_ivt+0x2400 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x2400 Entry 9 (size 64 bundles) Instruction Access-bit (27) +ENTRY(iaccess_bit) +#ifdef XEN + REFLECT(9) +#endif + DBG_FAULT(9) + // Like Entry 8, except for instruction access + mov r16=cr.ifa // get the address that caused the fault + movl r30=1f // load continuation point in case of nested fault + mov r31=pr // save predicates +#ifdef CONFIG_ITANIUM + /* + * Erratum 10 (IFA may contain incorrect address) has "NoFix" status. + */ + mov r17=cr.ipsr + ;; + mov r18=cr.iip + tbit.z p6,p0=r17,IA64_PSR_IS_BIT // IA64 instruction set? + ;; +(p6) mov r16=r18 // if so, use cr.iip instead of cr.ifa +#endif /* CONFIG_ITANIUM */ + ;; + thash r17=r16 // compute virtual address of L3 PTE + mov r29=b0 // save b0 in case of nested fault) +#ifdef CONFIG_SMP + mov r28=ar.ccv // save ar.ccv + ;; +1: ld8 r18=[r17] + ;; + mov ar.ccv=r18 // set compare value for cmpxchg + or r25=_PAGE_A,r18 // set the accessed bit + ;; + cmpxchg8.acq r26=[r17],r25,ar.ccv + mov r24=PAGE_SHIFT<<2 + ;; + cmp.eq p6,p7=r26,r18 + ;; +(p6) itc.i r25 // install updated PTE + ;; + /* + * Tell the assemblers dependency-violation checker that the above "itc" instructions + * cannot possibly affect the following loads: + */ + dv_serialize_data + + ld8 r18=[r17] // read PTE again + ;; + cmp.eq p6,p7=r18,r25 // is it same as the newly installed + ;; +(p7) ptc.l r16,r24 + mov b0=r29 // restore b0 + mov ar.ccv=r28 +#else /* !CONFIG_SMP */ + ;; +1: ld8 r18=[r17] + ;; + or r18=_PAGE_A,r18 // set the accessed bit + mov b0=r29 // restore b0 + ;; + st8 [r17]=r18 // store back updated PTE + itc.i r18 // install updated PTE +#endif /* !CONFIG_SMP */ + mov pr=r31,-1 + rfi +END(iaccess_bit) + + .org ia64_ivt+0x2800 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x2800 Entry 10 (size 64 bundles) Data Access-bit (15,55) +ENTRY(daccess_bit) +#ifdef XEN + REFLECT(10) +#endif + DBG_FAULT(10) + // Like Entry 8, except for data access + mov r16=cr.ifa // get the address that caused the fault + movl r30=1f // load continuation point in case of nested fault + ;; + thash r17=r16 // compute virtual address of L3 PTE + mov r31=pr + mov r29=b0 // save b0 in case of nested fault) +#ifdef CONFIG_SMP + mov r28=ar.ccv // save ar.ccv + ;; +1: ld8 r18=[r17] + ;; // avoid RAW on r18 + mov ar.ccv=r18 // set compare value for cmpxchg + or r25=_PAGE_A,r18 // set the dirty bit + ;; + cmpxchg8.acq r26=[r17],r25,ar.ccv + mov r24=PAGE_SHIFT<<2 + ;; + cmp.eq p6,p7=r26,r18 + ;; +(p6) itc.d r25 // install updated PTE + /* + * Tell the assemblers dependency-violation checker that the above "itc" instructions + * cannot possibly affect the following loads: + */ + dv_serialize_data + ;; + ld8 r18=[r17] // read PTE again + ;; + cmp.eq p6,p7=r18,r25 // is it same as the newly installed + ;; +(p7) ptc.l r16,r24 + mov ar.ccv=r28 +#else + ;; +1: ld8 r18=[r17] + ;; // avoid RAW on r18 + or r18=_PAGE_A,r18 // set the accessed bit + ;; + st8 [r17]=r18 // store back updated PTE + itc.d r18 // install updated PTE +#endif + mov b0=r29 // restore b0 + mov pr=r31,-1 + rfi +END(daccess_bit) + + .org ia64_ivt+0x2c00 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x2c00 Entry 11 (size 64 bundles) Break instruction (33) +ENTRY(break_fault) + /* + * The streamlined system call entry/exit paths only save/restore the initial part + * of pt_regs. This implies that the callers of system-calls must adhere to the + * normal procedure calling conventions. + * + * Registers to be saved & restored: + * CR registers: cr.ipsr, cr.iip, cr.ifs + * AR registers: ar.unat, ar.pfs, ar.rsc, ar.rnat, ar.bspstore, ar.fpsr + * others: pr, b0, b6, loadrs, r1, r11, r12, r13, r15 + * Registers to be restored only: + * r8-r11: output value from the system call. + * + * During system call exit, scratch registers (including r15) are modified/cleared + * to prevent leaking bits from kernel to user level. + */ + DBG_FAULT(11) +#ifdef XEN + mov r16=cr.isr + mov r17=cr.iim + mov r31=pr + ;; + cmp.eq p7,p0=r0,r17 // is this a psuedo-cover? + // FIXME: may also need to check slot==2? +(p7) br.sptk.many dispatch_privop_fault + br.sptk.many dispatch_break_fault +#endif + mov r16=IA64_KR(CURRENT) // r16 = current task; 12 cycle read lat. + mov r17=cr.iim + mov r18=__IA64_BREAK_SYSCALL + mov r21=ar.fpsr + mov r29=cr.ipsr + mov r19=b6 + mov r25=ar.unat + mov r27=ar.rsc + mov r26=ar.pfs + mov r28=cr.iip +#ifndef XEN + mov r31=pr // prepare to save predicates +#endif + mov r20=r1 + ;; + adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16 + cmp.eq p0,p7=r18,r17 // is this a system call? (p7 <- false, if so) +(p7) br.cond.spnt non_syscall + ;; + ld1 r17=[r16] // load current->thread.on_ustack flag + st1 [r16]=r0 // clear current->thread.on_ustack flag + add r1=-IA64_TASK_THREAD_ON_USTACK_OFFSET,r16 // set r1 for MINSTATE_START_SAVE_MIN_VIRT + ;; + invala + + /* adjust return address so we skip over the break instruction: */ + + extr.u r8=r29,41,2 // extract ei field from cr.ipsr + ;; + cmp.eq p6,p7=2,r8 // isr.ei==2? + mov r2=r1 // setup r2 for ia64_syscall_setup + ;; +(p6) mov r8=0 // clear ei to 0 +(p6) adds r28=16,r28 // switch cr.iip to next bundle cr.ipsr.ei wrapped +(p7) adds r8=1,r8 // increment ei to next slot + ;; + cmp.eq pKStk,pUStk=r0,r17 // are we in kernel mode already? + dep r29=r8,r29,41,2 // insert new ei into cr.ipsr + ;; + + // switch from user to kernel RBS: + MINSTATE_START_SAVE_MIN_VIRT + br.call.sptk.many b7=ia64_syscall_setup + ;; + MINSTATE_END_SAVE_MIN_VIRT // switch to bank 1 + ssm psr.ic | PSR_DEFAULT_BITS + ;; + srlz.i // guarantee that interruption collection is on + mov r3=NR_syscalls - 1 + ;; +(p15) ssm psr.i // restore psr.i + // p10==true means out registers are more than 8 or r15's Nat is true +(p10) br.cond.spnt.many ia64_ret_from_syscall + ;; + movl r16=sys_call_table + + adds r15=-1024,r15 // r15 contains the syscall number---subtract 1024 + movl r2=ia64_ret_from_syscall + ;; + shladd r20=r15,3,r16 // r20 = sys_call_table + 8*(syscall-1024) + cmp.leu p6,p7=r15,r3 // (syscall > 0 && syscall < 1024 + NR_syscalls) ? + mov rp=r2 // set the real return addr + ;; +(p6) ld8 r20=[r20] // load address of syscall entry point +(p7) movl r20=sys_ni_syscall + + add r2=TI_FLAGS+IA64_TASK_SIZE,r13 + ;; + ld4 r2=[r2] // r2 = current_thread_info()->flags + ;; + and r2=_TIF_SYSCALL_TRACEAUDIT,r2 // mask trace or audit + ;; + cmp.eq p8,p0=r2,r0 + mov b6=r20 + ;; +(p8) br.call.sptk.many b6=b6 // ignore this return addr + br.cond.sptk ia64_trace_syscall + // NOT REACHED +END(break_fault) + + .org ia64_ivt+0x3000 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x3000 Entry 12 (size 64 bundles) External Interrupt (4) +ENTRY(interrupt) + DBG_FAULT(12) + mov r31=pr // prepare to save predicates + ;; + SAVE_MIN_WITH_COVER // uses r31; defines r2 and r3 + ssm psr.ic | PSR_DEFAULT_BITS + ;; + adds r3=8,r2 // set up second base pointer for SAVE_REST + srlz.i // ensure everybody knows psr.ic is back on + ;; + SAVE_REST + ;; + alloc r14=ar.pfs,0,0,2,0 // must be first in an insn group + mov out0=cr.ivr // pass cr.ivr as first arg + add out1=16,sp // pass pointer to pt_regs as second arg + ;; + srlz.d // make sure we see the effect of cr.ivr + movl r14=ia64_leave_kernel + ;; + mov rp=r14 + br.call.sptk.many b6=ia64_handle_irq +END(interrupt) + + .org ia64_ivt+0x3400 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x3400 Entry 13 (size 64 bundles) Reserved + DBG_FAULT(13) + FAULT(13) + +#ifdef XEN + // There is no particular reason for this code to be here, other than that + // there happens to be space here that would go unused otherwise. If this + // fault ever gets "unreserved", simply moved the following code to a more + // suitable spot... + +ENTRY(dispatch_break_fault) + SAVE_MIN_WITH_COVER + ;; + alloc r14=ar.pfs,0,0,4,0 // now it's safe (must be first in insn group!) + mov out0=cr.ifa + adds out1=16,sp + mov out2=cr.isr // FIXME: pity to make this slow access twice + mov out3=cr.iim // FIXME: pity to make this slow access twice + + ssm psr.ic | PSR_DEFAULT_BITS + ;; + srlz.i // guarantee that interruption collection is on + ;; +(p15) ssm psr.i // restore psr.i + adds r3=8,r2 // set up second base pointer + ;; + SAVE_REST + movl r14=ia64_leave_kernel + ;; + mov rp=r14 + br.sptk.many ia64_prepare_handle_break +END(dispatch_break_fault) +#endif + + .org ia64_ivt+0x3800 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x3800 Entry 14 (size 64 bundles) Reserved + DBG_FAULT(14) + FAULT(14) + + /* + * There is no particular reason for this code to be here, other than that + * there happens to be space here that would go unused otherwise. If this + * fault ever gets "unreserved", simply moved the following code to a more + * suitable spot... + * + * ia64_syscall_setup() is a separate subroutine so that it can + * allocate stacked registers so it can safely demine any + * potential NaT values from the input registers. + * + * On entry: + * - executing on bank 0 or bank 1 register set (doesn't matter) + * - r1: stack pointer + * - r2: current task pointer + * - r3: preserved + * - r11: original contents (saved ar.pfs to be saved) + * - r12: original contents (sp to be saved) + * - r13: original contents (tp to be saved) + * - r15: original contents (syscall # to be saved) + * - r18: saved bsp (after switching to kernel stack) + * - r19: saved b6 + * - r20: saved r1 (gp) + * - r21: saved ar.fpsr + * - r22: kernel's register backing store base (krbs_base) + * - r23: saved ar.bspstore + * - r24: saved ar.rnat + * - r25: saved ar.unat + * - r26: saved ar.pfs + * - r27: saved ar.rsc + * - r28: saved cr.iip + * - r29: saved cr.ipsr + * - r31: saved pr + * - b0: original contents (to be saved) + * On exit: + * - executing on bank 1 registers + * - psr.ic enabled, interrupts restored + * - p10: TRUE if syscall is invoked with more than 8 out + * registers or r15's Nat is true + * - r1: kernel's gp + * - r3: preserved (same as on entry) + * - r8: -EINVAL if p10 is true + * - r12: points to kernel stack + * - r13: points to current task + * - p15: TRUE if interrupts need to be re-enabled + * - ar.fpsr: set to kernel settings + */ +GLOBAL_ENTRY(ia64_syscall_setup) +#ifndef XEN +#if PT(B6) != 0 +# error This code assumes that b6 is the first field in pt_regs. +#endif +#endif + st8 [r1]=r19 // save b6 + add r16=PT(CR_IPSR),r1 // initialize first base pointer + add r17=PT(R11),r1 // initialize second base pointer + ;; + alloc r19=ar.pfs,8,0,0,0 // ensure in0-in7 are writable + st8 [r16]=r29,PT(AR_PFS)-PT(CR_IPSR) // save cr.ipsr + tnat.nz p8,p0=in0 + + st8.spill [r17]=r11,PT(CR_IIP)-PT(R11) // save r11 + tnat.nz p9,p0=in1 +(pKStk) mov r18=r0 // make sure r18 isn't NaT + ;; + + st8 [r16]=r26,PT(CR_IFS)-PT(AR_PFS) // save ar.pfs + st8 [r17]=r28,PT(AR_UNAT)-PT(CR_IIP) // save cr.iip + mov r28=b0 // save b0 (2 cyc) + ;; + + st8 [r17]=r25,PT(AR_RSC)-PT(AR_UNAT) // save ar.unat + dep r19=0,r19,38,26 // clear all bits but 0..37 [I0] +(p8) mov in0=-1 + ;; + + st8 [r16]=r19,PT(AR_RNAT)-PT(CR_IFS) // store ar.pfs.pfm in cr.ifs + extr.u r11=r19,7,7 // I0 // get sol of ar.pfs + and r8=0x7f,r19 // A // get sof of ar.pfs + + st8 [r17]=r27,PT(AR_BSPSTORE)-PT(AR_RSC)// save ar.rsc + tbit.nz p15,p0=r29,IA64_PSR_I_BIT // I0 +(p9) mov in1=-1 + ;; + +(pUStk) sub r18=r18,r22 // r18=RSE.ndirty*8 + tnat.nz p10,p0=in2 + add r11=8,r11 + ;; +(pKStk) adds r16=PT(PR)-PT(AR_RNAT),r16 // skip over ar_rnat field +(pKStk) adds r17=PT(B0)-PT(AR_BSPSTORE),r17 // skip over ar_bspstore field + tnat.nz p11,p0=in3 + ;; +(p10) mov in2=-1 + tnat.nz p12,p0=in4 // [I0] +(p11) mov in3=-1 + ;; +(pUStk) st8 [r16]=r24,PT(PR)-PT(AR_RNAT) // save ar.rnat +(pUStk) st8 [r17]=r23,PT(B0)-PT(AR_BSPSTORE) // save ar.bspstore + shl r18=r18,16 // compute ar.rsc to be used for "loadrs" + ;; + st8 [r16]=r31,PT(LOADRS)-PT(PR) // save predicates + st8 [r17]=r28,PT(R1)-PT(B0) // save b0 + tnat.nz p13,p0=in5 // [I0] + ;; + st8 [r16]=r18,PT(R12)-PT(LOADRS) // save ar.rsc value for "loadrs" + st8.spill [r17]=r20,PT(R13)-PT(R1) // save original r1 +(p12) mov in4=-1 + ;; + +.mem.offset 0,0; st8.spill [r16]=r12,PT(AR_FPSR)-PT(R12) // save r12 +.mem.offset 8,0; st8.spill [r17]=r13,PT(R15)-PT(R13) // save r13 +(p13) mov in5=-1 + ;; + st8 [r16]=r21,PT(R8)-PT(AR_FPSR) // save ar.fpsr + tnat.nz p14,p0=in6 + cmp.lt p10,p9=r11,r8 // frame size can't be more than local+8 + ;; + stf8 [r16]=f1 // ensure pt_regs.r8 != 0 (see handle_syscall_error) +(p9) tnat.nz p10,p0=r15 + adds r12=-16,r1 // switch to kernel memory stack (with 16 bytes of scratch) + + st8.spill [r17]=r15 // save r15 + tnat.nz p8,p0=in7 + nop.i 0 + + mov r13=r2 // establish `current' + movl r1=__gp // establish kernel global pointer + ;; +(p14) mov in6=-1 +(p8) mov in7=-1 + nop.i 0 + + cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0 + movl r17=FPSR_DEFAULT + ;; + mov.m ar.fpsr=r17 // set ar.fpsr to kernel default value +(p10) mov r8=-EINVAL + br.ret.sptk.many b7 +END(ia64_syscall_setup) + + .org ia64_ivt+0x3c00 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x3c00 Entry 15 (size 64 bundles) Reserved + DBG_FAULT(15) + FAULT(15) + + /* + * Squatting in this space ... + * + * This special case dispatcher for illegal operation faults allows preserved + * registers to be modified through a callback function (asm only) that is handed + * back from the fault handler in r8. Up to three arguments can be passed to the + * callback function by returning an aggregate with the callback as its first + * element, followed by the arguments. + */ +ENTRY(dispatch_illegal_op_fault) + SAVE_MIN_WITH_COVER + ssm psr.ic | PSR_DEFAULT_BITS + ;; + srlz.i // guarantee that interruption collection is on + ;; +(p15) ssm psr.i // restore psr.i + adds r3=8,r2 // set up second base pointer for SAVE_REST + ;; + alloc r14=ar.pfs,0,0,1,0 // must be first in insn group + mov out0=ar.ec + ;; + SAVE_REST + ;; + br.call.sptk.many rp=ia64_illegal_op_fault +.ret0: ;; + alloc r14=ar.pfs,0,0,3,0 // must be first in insn group + mov out0=r9 + mov out1=r10 + mov out2=r11 + movl r15=ia64_leave_kernel + ;; + mov rp=r15 + mov b6=r8 + ;; + cmp.ne p6,p0=0,r8 +(p6) br.call.dpnt.many b6=b6 // call returns to ia64_leave_kernel + br.sptk.many ia64_leave_kernel +END(dispatch_illegal_op_fault) + + .org ia64_ivt+0x4000 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x4000 Entry 16 (size 64 bundles) Reserved + DBG_FAULT(16) + FAULT(16) + +#ifdef XEN + // There is no particular reason for this code to be here, other than that + // there happens to be space here that would go unused otherwise. If this + // fault ever gets "unreserved", simply moved the following code to a more + // suitable spot... + +ENTRY(dispatch_privop_fault) + SAVE_MIN_WITH_COVER + ;; + alloc r14=ar.pfs,0,0,4,0 // now it's safe (must be first in insn group!) + mov out0=cr.ifa + adds out1=16,sp + mov out2=cr.isr // FIXME: pity to make this slow access twice + mov out3=cr.itir + + ssm psr.ic | PSR_DEFAULT_BITS + ;; + srlz.i // guarantee that interruption collection is on + ;; +(p15) ssm psr.i // restore psr.i + adds r3=8,r2 // set up second base pointer + ;; + SAVE_REST + movl r14=ia64_leave_kernel + ;; + mov rp=r14 + br.sptk.many ia64_prepare_handle_privop +END(dispatch_privop_fault) +#endif + + + .org ia64_ivt+0x4400 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x4400 Entry 17 (size 64 bundles) Reserved + DBG_FAULT(17) + FAULT(17) + +ENTRY(non_syscall) + SAVE_MIN_WITH_COVER + + // There is no particular reason for this code to be here, other than that + // there happens to be space here that would go unused otherwise. If this + // fault ever gets "unreserved", simply moved the following code to a more + // suitable spot... + + alloc r14=ar.pfs,0,0,2,0 + mov out0=cr.iim + add out1=16,sp + adds r3=8,r2 // set up second base pointer for SAVE_REST + + ssm psr.ic | PSR_DEFAULT_BITS + ;; + srlz.i // guarantee that interruption collection is on + ;; +(p15) ssm psr.i // restore psr.i + movl r15=ia64_leave_kernel + ;; + SAVE_REST + mov rp=r15 + ;; + br.call.sptk.many b6=ia64_bad_break // avoid WAW on CFM and ignore return addr +END(non_syscall) + + .org ia64_ivt+0x4800 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x4800 Entry 18 (size 64 bundles) Reserved + DBG_FAULT(18) + FAULT(18) + + /* + * There is no particular reason for this code to be here, other than that + * there happens to be space here that would go unused otherwise. If this + * fault ever gets "unreserved", simply moved the following code to a more + * suitable spot... + */ + +ENTRY(dispatch_unaligned_handler) + SAVE_MIN_WITH_COVER + ;; + alloc r14=ar.pfs,0,0,2,0 // now it's safe (must be first in insn group!) + mov out0=cr.ifa + adds out1=16,sp + + ssm psr.ic | PSR_DEFAULT_BITS + ;; + srlz.i // guarantee that interruption collection is on + ;; +(p15) ssm psr.i // restore psr.i + adds r3=8,r2 // set up second base pointer + ;; + SAVE_REST + movl r14=ia64_leave_kernel + ;; + mov rp=r14 + br.sptk.many ia64_prepare_handle_unaligned +END(dispatch_unaligned_handler) + + .org ia64_ivt+0x4c00 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x4c00 Entry 19 (size 64 bundles) Reserved + DBG_FAULT(19) + FAULT(19) + + /* + * There is no particular reason for this code to be here, other than that + * there happens to be space here that would go unused otherwise. If this + * fault ever gets "unreserved", simply moved the following code to a more + * suitable spot... + */ + +ENTRY(dispatch_to_fault_handler) + /* + * Input: + * psr.ic: off + * r19: fault vector number (e.g., 24 for General Exception) + * r31: contains saved predicates (pr) + */ + SAVE_MIN_WITH_COVER_R19 + alloc r14=ar.pfs,0,0,5,0 + mov out0=r15 + mov out1=cr.isr + mov out2=cr.ifa + mov out3=cr.iim + mov out4=cr.itir + ;; + ssm psr.ic | PSR_DEFAULT_BITS + ;; + srlz.i // guarantee that interruption collection is on + ;; +(p15) ssm psr.i // restore psr.i + adds r3=8,r2 // set up second base pointer for SAVE_REST + ;; + SAVE_REST + movl r14=ia64_leave_kernel + ;; + mov rp=r14 + br.call.sptk.many b6=ia64_fault +END(dispatch_to_fault_handler) + +// +// --- End of long entries, Beginning of short entries +// + + .org ia64_ivt+0x5000 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x5000 Entry 20 (size 16 bundles) Page Not Present (10,22,49) +ENTRY(page_not_present) +#ifdef XEN + REFLECT(20) +#endif + DBG_FAULT(20) + mov r16=cr.ifa + rsm psr.dt + /* + * The Linux page fault handler doesn't expect non-present pages to be in + * the TLB. Flush the existing entry now, so we meet that expectation. + */ + mov r17=PAGE_SHIFT<<2 + ;; + ptc.l r16,r17 + ;; + mov r31=pr + srlz.d + br.sptk.many page_fault +END(page_not_present) + + .org ia64_ivt+0x5100 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x5100 Entry 21 (size 16 bundles) Key Permission (13,25,52) +ENTRY(key_permission) +#ifdef XEN + REFLECT(21) +#endif + DBG_FAULT(21) + mov r16=cr.ifa + rsm psr.dt + mov r31=pr + ;; + srlz.d + br.sptk.many page_fault +END(key_permission) + + .org ia64_ivt+0x5200 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x5200 Entry 22 (size 16 bundles) Instruction Access Rights (26) +ENTRY(iaccess_rights) +#ifdef XEN + REFLECT(22) +#endif + DBG_FAULT(22) + mov r16=cr.ifa + rsm psr.dt + mov r31=pr + ;; + srlz.d + br.sptk.many page_fault +END(iaccess_rights) + + .org ia64_ivt+0x5300 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x5300 Entry 23 (size 16 bundles) Data Access Rights (14,53) +ENTRY(daccess_rights) +#ifdef XEN + REFLECT(23) +#endif + DBG_FAULT(23) + mov r16=cr.ifa + rsm psr.dt + mov r31=pr + ;; + srlz.d + br.sptk.many page_fault +END(daccess_rights) + + .org ia64_ivt+0x5400 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x5400 Entry 24 (size 16 bundles) General Exception (5,32,34,36,38,39) +ENTRY(general_exception) + DBG_FAULT(24) + mov r16=cr.isr + mov r31=pr + ;; +#ifdef XEN + cmp4.ge p6,p0=0x20,r16 +(p6) br.sptk.many dispatch_privop_fault +#else + cmp4.eq p6,p0=0,r16 +(p6) br.sptk.many dispatch_illegal_op_fault +#endif + ;; + mov r19=24 // fault number + br.sptk.many dispatch_to_fault_handler +END(general_exception) + + .org ia64_ivt+0x5500 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x5500 Entry 25 (size 16 bundles) Disabled FP-Register (35) +ENTRY(disabled_fp_reg) +#ifdef XEN + REFLECT(25) +#endif + DBG_FAULT(25) + rsm psr.dfh // ensure we can access fph + ;; + srlz.d + mov r31=pr + mov r19=25 + br.sptk.many dispatch_to_fault_handler +END(disabled_fp_reg) + + .org ia64_ivt+0x5600 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x5600 Entry 26 (size 16 bundles) Nat Consumption (11,23,37,50) +ENTRY(nat_consumption) +#ifdef XEN + REFLECT(26) +#endif + DBG_FAULT(26) + FAULT(26) +END(nat_consumption) + + .org ia64_ivt+0x5700 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x5700 Entry 27 (size 16 bundles) Speculation (40) +ENTRY(speculation_vector) +#ifdef XEN + // this probably need not reflect... + REFLECT(27) +#endif + DBG_FAULT(27) + /* + * A [f]chk.[as] instruction needs to take the branch to the recovery code but + * this part of the architecture is not implemented in hardware on some CPUs, such + * as Itanium. Thus, in general we need to emulate the behavior. IIM contains + * the relative target (not yet sign extended). So after sign extending it we + * simply add it to IIP. We also need to reset the EI field of the IPSR to zero, + * i.e., the slot to restart into. + * + * cr.imm contains zero_ext(imm21) + */ + mov r18=cr.iim + ;; + mov r17=cr.iip + shl r18=r18,43 // put sign bit in position (43=64-21) + ;; + + mov r16=cr.ipsr + shr r18=r18,39 // sign extend (39=43-4) + ;; + + add r17=r17,r18 // now add the offset + ;; + mov cr.iip=r17 + dep r16=0,r16,41,2 // clear EI + ;; + + mov cr.ipsr=r16 + ;; + + rfi // and go back +END(speculation_vector) + + .org ia64_ivt+0x5800 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x5800 Entry 28 (size 16 bundles) Reserved + DBG_FAULT(28) + FAULT(28) + + .org ia64_ivt+0x5900 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x5900 Entry 29 (size 16 bundles) Debug (16,28,56) +ENTRY(debug_vector) +#ifdef XEN + REFLECT(29) +#endif + DBG_FAULT(29) + FAULT(29) +END(debug_vector) + + .org ia64_ivt+0x5a00 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x5a00 Entry 30 (size 16 bundles) Unaligned Reference (57) +ENTRY(unaligned_access) +#ifdef XEN + REFLECT(30) +#endif + DBG_FAULT(30) + mov r16=cr.ipsr + mov r31=pr // prepare to save predicates + ;; + br.sptk.many dispatch_unaligned_handler +END(unaligned_access) + + .org ia64_ivt+0x5b00 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x5b00 Entry 31 (size 16 bundles) Unsupported Data Reference (57) +ENTRY(unsupported_data_reference) +#ifdef XEN + REFLECT(31) +#endif + DBG_FAULT(31) + FAULT(31) +END(unsupported_data_reference) + + .org ia64_ivt+0x5c00 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x5c00 Entry 32 (size 16 bundles) Floating-Point Fault (64) +ENTRY(floating_point_fault) +#ifdef XEN + REFLECT(32) +#endif + DBG_FAULT(32) + FAULT(32) +END(floating_point_fault) + + .org ia64_ivt+0x5d00 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x5d00 Entry 33 (size 16 bundles) Floating Point Trap (66) +ENTRY(floating_point_trap) +#ifdef XEN + REFLECT(33) +#endif + DBG_FAULT(33) + FAULT(33) +END(floating_point_trap) + + .org ia64_ivt+0x5e00 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x5e00 Entry 34 (size 16 bundles) Lower Privilege Transfer Trap (66) +ENTRY(lower_privilege_trap) +#ifdef XEN + REFLECT(34) +#endif + DBG_FAULT(34) + FAULT(34) +END(lower_privilege_trap) + + .org ia64_ivt+0x5f00 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x5f00 Entry 35 (size 16 bundles) Taken Branch Trap (68) +ENTRY(taken_branch_trap) +#ifdef XEN + REFLECT(35) +#endif + DBG_FAULT(35) + FAULT(35) +END(taken_branch_trap) + + .org ia64_ivt+0x6000 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x6000 Entry 36 (size 16 bundles) Single Step Trap (69) +ENTRY(single_step_trap) +#ifdef XEN + REFLECT(36) +#endif + DBG_FAULT(36) + FAULT(36) +END(single_step_trap) + + .org ia64_ivt+0x6100 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x6100 Entry 37 (size 16 bundles) Reserved + DBG_FAULT(37) + FAULT(37) + + .org ia64_ivt+0x6200 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x6200 Entry 38 (size 16 bundles) Reserved + DBG_FAULT(38) + FAULT(38) + + .org ia64_ivt+0x6300 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x6300 Entry 39 (size 16 bundles) Reserved + DBG_FAULT(39) + FAULT(39) + + .org ia64_ivt+0x6400 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x6400 Entry 40 (size 16 bundles) Reserved + DBG_FAULT(40) + FAULT(40) + + .org ia64_ivt+0x6500 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x6500 Entry 41 (size 16 bundles) Reserved + DBG_FAULT(41) + FAULT(41) + + .org ia64_ivt+0x6600 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x6600 Entry 42 (size 16 bundles) Reserved + DBG_FAULT(42) + FAULT(42) + + .org ia64_ivt+0x6700 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x6700 Entry 43 (size 16 bundles) Reserved + DBG_FAULT(43) + FAULT(43) + + .org ia64_ivt+0x6800 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x6800 Entry 44 (size 16 bundles) Reserved + DBG_FAULT(44) + FAULT(44) + + .org ia64_ivt+0x6900 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x6900 Entry 45 (size 16 bundles) IA-32 Exeception (17,18,29,41,42,43,44,58,60,61,62,72,73,75,76,77) +ENTRY(ia32_exception) +#ifdef XEN + REFLECT(45) +#endif + DBG_FAULT(45) + FAULT(45) +END(ia32_exception) + + .org ia64_ivt+0x6a00 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x6a00 Entry 46 (size 16 bundles) IA-32 Intercept (30,31,59,70,71) +ENTRY(ia32_intercept) +#ifdef XEN + REFLECT(46) +#endif + DBG_FAULT(46) +#ifdef CONFIG_IA32_SUPPORT + mov r31=pr + mov r16=cr.isr + ;; + extr.u r17=r16,16,8 // get ISR.code + mov r18=ar.eflag + mov r19=cr.iim // old eflag value + ;; + cmp.ne p6,p0=2,r17 +(p6) br.cond.spnt 1f // not a system flag fault + xor r16=r18,r19 + ;; + extr.u r17=r16,18,1 // get the eflags.ac bit + ;; + cmp.eq p6,p0=0,r17 +(p6) br.cond.spnt 1f // eflags.ac bit didn't change + ;; + mov pr=r31,-1 // restore predicate registers + rfi + +1: +#endif // CONFIG_IA32_SUPPORT + FAULT(46) +END(ia32_intercept) + + .org ia64_ivt+0x6b00 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x6b00 Entry 47 (size 16 bundles) IA-32 Interrupt (74) +ENTRY(ia32_interrupt) +#ifdef XEN + REFLECT(47) +#endif + DBG_FAULT(47) +#ifdef CONFIG_IA32_SUPPORT + mov r31=pr + br.sptk.many dispatch_to_ia32_handler +#else + FAULT(47) +#endif +END(ia32_interrupt) + + .org ia64_ivt+0x6c00 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x6c00 Entry 48 (size 16 bundles) Reserved + DBG_FAULT(48) + FAULT(48) + + .org ia64_ivt+0x6d00 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x6d00 Entry 49 (size 16 bundles) Reserved + DBG_FAULT(49) + FAULT(49) + + .org ia64_ivt+0x6e00 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x6e00 Entry 50 (size 16 bundles) Reserved + DBG_FAULT(50) + FAULT(50) + + .org ia64_ivt+0x6f00 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x6f00 Entry 51 (size 16 bundles) Reserved + DBG_FAULT(51) + FAULT(51) + + .org ia64_ivt+0x7000 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x7000 Entry 52 (size 16 bundles) Reserved + DBG_FAULT(52) + FAULT(52) + + .org ia64_ivt+0x7100 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x7100 Entry 53 (size 16 bundles) Reserved + DBG_FAULT(53) + FAULT(53) + + .org ia64_ivt+0x7200 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x7200 Entry 54 (size 16 bundles) Reserved + DBG_FAULT(54) + FAULT(54) + + .org ia64_ivt+0x7300 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x7300 Entry 55 (size 16 bundles) Reserved + DBG_FAULT(55) + FAULT(55) + + .org ia64_ivt+0x7400 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x7400 Entry 56 (size 16 bundles) Reserved + DBG_FAULT(56) + FAULT(56) + + .org ia64_ivt+0x7500 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x7500 Entry 57 (size 16 bundles) Reserved + DBG_FAULT(57) + FAULT(57) + + .org ia64_ivt+0x7600 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x7600 Entry 58 (size 16 bundles) Reserved + DBG_FAULT(58) + FAULT(58) + + .org ia64_ivt+0x7700 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x7700 Entry 59 (size 16 bundles) Reserved + DBG_FAULT(59) + FAULT(59) + + .org ia64_ivt+0x7800 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x7800 Entry 60 (size 16 bundles) Reserved + DBG_FAULT(60) + FAULT(60) + + .org ia64_ivt+0x7900 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x7900 Entry 61 (size 16 bundles) Reserved + DBG_FAULT(61) + FAULT(61) + + .org ia64_ivt+0x7a00 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x7a00 Entry 62 (size 16 bundles) Reserved + DBG_FAULT(62) + FAULT(62) + + .org ia64_ivt+0x7b00 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x7b00 Entry 63 (size 16 bundles) Reserved + DBG_FAULT(63) + FAULT(63) + + .org ia64_ivt+0x7c00 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x7c00 Entry 64 (size 16 bundles) Reserved + DBG_FAULT(64) + FAULT(64) + + .org ia64_ivt+0x7d00 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x7d00 Entry 65 (size 16 bundles) Reserved + DBG_FAULT(65) + FAULT(65) + + .org ia64_ivt+0x7e00 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x7e00 Entry 66 (size 16 bundles) Reserved + DBG_FAULT(66) + FAULT(66) + + .org ia64_ivt+0x7f00 +///////////////////////////////////////////////////////////////////////////////////////// +// 0x7f00 Entry 67 (size 16 bundles) Reserved + DBG_FAULT(67) + FAULT(67) + +#ifdef XEN + .org ia64_ivt+0x8000 +ENTRY(dispatch_reflection) + /* + * Input: + * psr.ic: off + * r19: intr type (offset into ivt, see ia64_int.h) + * r31: contains saved predicates (pr) + */ + SAVE_MIN_WITH_COVER_R19 + alloc r14=ar.pfs,0,0,5,0 + mov out4=r15 + mov out0=cr.ifa + adds out1=16,sp + mov out2=cr.isr + mov out3=cr.iim +// mov out3=cr.itir + + ssm psr.ic | PSR_DEFAULT_BITS + ;; + srlz.i // guarantee that interruption collection is on + ;; +(p15) ssm psr.i // restore psr.i + adds r3=8,r2 // set up second base pointer + ;; + SAVE_REST + movl r14=ia64_leave_kernel + ;; + mov rp=r14 + br.sptk.many ia64_prepare_handle_reflection +END(dispatch_reflection) +#endif + +#ifdef CONFIG_IA32_SUPPORT + + /* + * There is no particular reason for this code to be here, other than that + * there happens to be space here that would go unused otherwise. If this + * fault ever gets "unreserved", simply moved the following code to a more + * suitable spot... + */ + + // IA32 interrupt entry point + +ENTRY(dispatch_to_ia32_handler) + SAVE_MIN + ;; + mov r14=cr.isr + ssm psr.ic | PSR_DEFAULT_BITS + ;; + srlz.i // guarantee that interruption collection is on + ;; +(p15) ssm psr.i + adds r3=8,r2 // Base pointer for SAVE_REST + ;; + SAVE_REST + ;; + mov r15=0x80 + shr r14=r14,16 // Get interrupt number + ;; + cmp.ne p6,p0=r14,r15 +(p6) br.call.dpnt.many b6=non_ia32_syscall + + adds r14=IA64_PT_REGS_R8_OFFSET + 16,sp // 16 byte hole per SW conventions + adds r15=IA64_PT_REGS_R1_OFFSET + 16,sp + ;; + cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0 + ld8 r8=[r14] // get r8 + ;; + st8 [r15]=r8 // save original EAX in r1 (IA32 procs don't use the GP) + ;; + alloc r15=ar.pfs,0,0,6,0 // must first in an insn group + ;; + ld4 r8=[r14],8 // r8 == eax (syscall number) + mov r15=IA32_NR_syscalls + ;; + cmp.ltu.unc p6,p7=r8,r15 + ld4 out1=[r14],8 // r9 == ecx + ;; + ld4 out2=[r14],8 // r10 == edx + ;; + ld4 out0=[r14] // r11 == ebx + adds r14=(IA64_PT_REGS_R13_OFFSET) + 16,sp + ;; + ld4 out5=[r14],PT(R14)-PT(R13) // r13 == ebp + ;; + ld4 out3=[r14],PT(R15)-PT(R14) // r14 == esi + adds r2=TI_FLAGS+IA64_TASK_SIZE,r13 + ;; + ld4 out4=[r14] // r15 == edi + movl r16=ia32_syscall_table + ;; +(p6) shladd r16=r8,3,r16 // force ni_syscall if not valid syscall number + ld4 r2=[r2] // r2 = current_thread_info()->flags + ;; + ld8 r16=[r16] + and r2=_TIF_SYSCALL_TRACEAUDIT,r2 // mask trace or audit + ;; + mov b6=r16 + movl r15=ia32_ret_from_syscall + cmp.eq p8,p0=r2,r0 + ;; + mov rp=r15 +(p8) br.call.sptk.many b6=b6 + br.cond.sptk ia32_trace_syscall + +non_ia32_syscall: + alloc r15=ar.pfs,0,0,2,0 + mov out0=r14 // interrupt # + add out1=16,sp // pointer to pt_regs + ;; // avoid WAW on CFM + br.call.sptk.many rp=ia32_bad_interrupt +.ret1: movl r15=ia64_leave_kernel + ;; + mov rp=r15 + br.ret.sptk.many rp +END(dispatch_to_ia32_handler) + +#endif /* CONFIG_IA32_SUPPORT */ diff --git a/xen/arch/ia64/patch/linux-2.6.11/bootmem.h b/xen/arch/ia64/patch/linux-2.6.11/bootmem.h deleted file mode 100644 index 9a63aa92af..0000000000 --- a/xen/arch/ia64/patch/linux-2.6.11/bootmem.h +++ /dev/null @@ -1,17 +0,0 @@ - bootmem.h | 2 ++ - 1 files changed, 2 insertions(+) - -Index: linux-2.6.11/include/linux/bootmem.h -=================================================================== ---- linux-2.6.11.orig/include/linux/bootmem.h 2005-03-02 01:38:25.000000000 -0600 -+++ linux-2.6.11/include/linux/bootmem.h 2005-03-19 12:39:36.915887729 -0600 -@@ -41,7 +41,9 @@ extern unsigned long __init init_bootmem - extern void __init free_bootmem (unsigned long addr, unsigned long size); - extern void * __init __alloc_bootmem (unsigned long size, unsigned long align, unsigned long goal); - #ifndef CONFIG_HAVE_ARCH_BOOTMEM_NODE -+#ifndef XEN - extern void __init reserve_bootmem (unsigned long addr, unsigned long size); -+#endif - #define alloc_bootmem(x) \ - __alloc_bootmem((x), SMP_CACHE_BYTES, __pa(MAX_DMA_ADDRESS)) - #define alloc_bootmem_low(x) \ diff --git a/xen/arch/ia64/patch/linux-2.6.11/efi.c b/xen/arch/ia64/patch/linux-2.6.11/efi.c index 8fb00fa453..11e65f091d 100644 --- a/xen/arch/ia64/patch/linux-2.6.11/efi.c +++ b/xen/arch/ia64/patch/linux-2.6.11/efi.c @@ -1,29 +1,6 @@ - efi.c | 32 ++++++++++++++++++++++++++++++++ - 1 files changed, 32 insertions(+) - -Index: linux-2.6.11-xendiffs/arch/ia64/kernel/efi.c -=================================================================== ---- linux-2.6.11-xendiffs.orig/arch/ia64/kernel/efi.c 2005-04-07 12:22:08.230781400 -0500 -+++ linux-2.6.11-xendiffs/arch/ia64/kernel/efi.c 2005-04-07 12:25:11.875195997 -0500 -@@ -25,6 +25,9 @@ - #include - #include - #include -+#ifdef XEN -+#include -+#endif - - #include - #include -@@ -218,6 +221,7 @@ efi_gettimeofday (struct timespec *ts) - if ((*efi.get_time)(&tm, NULL) != EFI_SUCCESS) - return; - -+ dummy(); - ts->tv_sec = mktime(tm.year, tm.month, tm.day, tm.hour, tm.minute, tm.second); - ts->tv_nsec = tm.nanosecond; - } -@@ -320,6 +324,10 @@ efi_memmap_walk (efi_freemem_callback_t +--- ../../linux-2.6.11/arch/ia64/kernel/efi.c 2005-03-02 00:37:47.000000000 -0700 ++++ arch/ia64/efi.c 2005-04-29 14:09:24.000000000 -0600 +@@ -320,6 +320,10 @@ if (!(md->attribute & EFI_MEMORY_WB)) continue; @@ -34,7 +11,7 @@ Index: linux-2.6.11-xendiffs/arch/ia64/kernel/efi.c /* * granule_addr is the base of md's first granule. * [granule_addr - first_non_wb_addr) is guaranteed to -@@ -719,6 +727,30 @@ efi_get_iobase (void) +@@ -719,6 +723,30 @@ return 0; } diff --git a/xen/arch/ia64/patch/linux-2.6.11/entry.S b/xen/arch/ia64/patch/linux-2.6.11/entry.S index 4d88e3d277..19217002a5 100644 --- a/xen/arch/ia64/patch/linux-2.6.11/entry.S +++ b/xen/arch/ia64/patch/linux-2.6.11/entry.S @@ -1,86 +1,34 @@ - entry.S | 86 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++- - 1 files changed, 85 insertions(+), 1 deletion(-) - -Index: linux-2.6.11-xendiffs/arch/ia64/kernel/entry.S -=================================================================== ---- linux-2.6.11-xendiffs.orig/arch/ia64/kernel/entry.S 2005-04-08 13:32:07.636308237 -0500 -+++ linux-2.6.11-xendiffs/arch/ia64/kernel/entry.S 2005-04-08 13:37:04.612542509 -0500 -@@ -35,7 +35,9 @@ - - #include - #include -+#ifndef XEN - #include -+#endif - #include - #include - #include -@@ -46,6 +48,25 @@ +--- ../../linux-2.6.11/arch/ia64/kernel/entry.S 2005-03-02 00:37:50.000000000 -0700 ++++ arch/ia64/entry.S 2005-04-29 14:54:13.000000000 -0600 +@@ -46,6 +46,7 @@ #include "minstate.h" -+#ifdef XEN -+#define sys_execve 0 -+#define do_fork 0 -+#define syscall_trace_enter 0 -+#define syscall_trace_leave 0 -+#define schedule 0 -+#define do_notify_resume_user 0 -+#define ia64_rt_sigsuspend 0 -+#define ia64_rt_sigreturn 0 -+#define ia64_handle_unaligned 0 -+#define errno 0 -+#define sys_ni_syscall 0 -+#define unw_init_frame_info 0 -+#define sys_call_table 0 -+#define do_sigdelayed 0 -+#endif -+ -+ /* -+ ++#ifndef XEN /* * execve() is special because in case of success, we need to * setup a null register window frame. -@@ -187,11 +208,14 @@ GLOBAL_ENTRY(ia64_switch_to) - DO_SAVE_SWITCH_STACK - .body +@@ -174,6 +175,7 @@ + mov rp=loc0 + br.ret.sptk.many rp + END(sys_clone) ++#endif /* !XEN */ -+#ifdef XEN -+//#undef IA64_TASK_THREAD_KSP_OFFSET -+//#define IA64_TASK_THREAD_KSP_OFFSET 0x38 - adds r22=IA64_TASK_THREAD_KSP_OFFSET,r13 + /* + * prev_task <- ia64_switch_to(struct task_struct *next) +@@ -191,7 +193,11 @@ movl r25=init_task mov r27=IA64_KR(CURRENT_STACK) adds r21=IA64_TASK_THREAD_KSP_OFFSET,in0 -- dep r20=0,in0,61,3 // physical address of "next" ++#ifdef XEN + dep r20=0,in0,60,4 // physical address of "next" - ;; - st8 [r22]=sp // save kernel stack pointer of old task - shr.u r26=r20,IA64_GRANULE_SHIFT -@@ -203,6 +227,22 @@ GLOBAL_ENTRY(ia64_switch_to) - (p6) cmp.eq p7,p6=r26,r27 - (p6) br.cond.dpnt .map - ;; +#else -+ adds r22=IA64_TASK_THREAD_KSP_OFFSET,r13 -+ mov r27=IA64_KR(CURRENT_STACK) -+ dep r20=0,in0,61,3 // physical address of "current" -+ ;; -+ st8 [r22]=sp // save kernel stack pointer of old task -+ shr.u r26=r20,IA64_GRANULE_SHIFT -+ adds r21=IA64_TASK_THREAD_KSP_OFFSET,in0 -+ ;; -+ /* -+ * If we've already mapped this task's page, we can skip doing it again. -+ */ -+ cmp.eq p7,p6=r26,r27 -+(p6) br.cond.dpnt .map -+ ;; + dep r20=0,in0,61,3 // physical address of "next" +#endif - .done: - (p6) ssm psr.ic // if we had to map, reenable the psr.ic bit FIRST!!! ;; -@@ -220,6 +260,16 @@ GLOBAL_ENTRY(ia64_switch_to) + st8 [r22]=sp // save kernel stack pointer of old task + shr.u r26=r20,IA64_GRANULE_SHIFT +@@ -220,6 +226,16 @@ br.ret.sptk.many rp // boogie on out in new context .map: @@ -97,7 +45,7 @@ Index: linux-2.6.11-xendiffs/arch/ia64/kernel/entry.S rsm psr.ic // interrupts (psr.i) are already disabled here movl r25=PAGE_KERNEL ;; -@@ -376,7 +426,11 @@ END(save_switch_stack) +@@ -376,7 +392,11 @@ * - b7 holds address to return to * - must not touch r8-r11 */ @@ -109,7 +57,23 @@ Index: linux-2.6.11-xendiffs/arch/ia64/kernel/entry.S .prologue .altrp b7 -@@ -604,6 +658,11 @@ GLOBAL_ENTRY(ia64_ret_from_clone) +@@ -470,6 +490,7 @@ + br.cond.sptk.many b7 + END(load_switch_stack) + ++#ifndef XEN + GLOBAL_ENTRY(__ia64_syscall) + .regstk 6,0,0,0 + mov r15=in5 // put syscall number in place +@@ -588,6 +609,7 @@ + } + .ret4: br.cond.sptk ia64_leave_kernel + END(ia64_strace_leave_kernel) ++#endif + + GLOBAL_ENTRY(ia64_ret_from_clone) + PT_REGS_UNWIND_INFO(0) +@@ -604,6 +626,11 @@ */ br.call.sptk.many rp=ia64_invoke_schedule_tail } @@ -121,7 +85,7 @@ Index: linux-2.6.11-xendiffs/arch/ia64/kernel/entry.S .ret8: adds r2=TI_FLAGS+IA64_TASK_SIZE,r13 ;; -@@ -614,6 +673,7 @@ GLOBAL_ENTRY(ia64_ret_from_clone) +@@ -614,6 +641,7 @@ ;; cmp.ne p6,p0=r2,r0 (p6) br.cond.spnt .strace_check_retval @@ -129,14 +93,11 @@ Index: linux-2.6.11-xendiffs/arch/ia64/kernel/entry.S ;; // added stop bits to prevent r8 dependency END(ia64_ret_from_clone) // fall through -@@ -700,9 +760,14 @@ ENTRY(ia64_leave_syscall) +@@ -700,19 +728,25 @@ .work_processed_syscall: adds r2=PT(LOADRS)+16,r12 adds r3=PT(AR_BSPSTORE)+16,r12 -+#ifdef XEN -+ mov r31=r0 -+ ;; -+#else ++#ifndef XEN adds r18=TI_FLAGS+IA64_TASK_SIZE,r13 ;; (p6) ld4 r31=[r18] // load current_thread_info()->flags @@ -144,7 +105,21 @@ Index: linux-2.6.11-xendiffs/arch/ia64/kernel/entry.S ld8 r19=[r2],PT(B6)-PT(LOADRS) // load ar.rsc value for "loadrs" mov b7=r0 // clear b7 ;; -@@ -757,7 +822,11 @@ ENTRY(ia64_leave_syscall) + ld8 r23=[r3],PT(R11)-PT(AR_BSPSTORE) // load ar.bspstore (may be garbage) + ld8 r18=[r2],PT(R9)-PT(B6) // load b6 ++#ifndef XEN + (p6) and r15=TIF_WORK_MASK,r31 // any work other than TIF_SYSCALL_TRACE? ++#endif + ;; + mov r16=ar.bsp // M2 get existing backing store pointer ++#ifndef XEN + (p6) cmp4.ne.unc p6,p0=r15, r0 // any special work pending? + (p6) br.cond.spnt .work_pending_syscall ++#endif + ;; + // start restoring the state saved on the kernel stack (struct pt_regs): + ld8 r9=[r2],PT(CR_IPSR)-PT(R9) +@@ -757,7 +791,11 @@ ;; ld8.fill r12=[r2] // restore r12 (sp) ld8.fill r15=[r3] // restore r15 @@ -156,7 +131,7 @@ Index: linux-2.6.11-xendiffs/arch/ia64/kernel/entry.S ;; (pUStk) ld4 r3=[r3] // r3 = cpu_data->phys_stacked_size_p8 (pUStk) st1 [r14]=r17 -@@ -814,9 +883,18 @@ GLOBAL_ENTRY(ia64_leave_kernel) +@@ -814,9 +852,18 @@ (pUStk) cmp.eq.unc p6,p0=r0,r0 // p6 <- pUStk #endif .work_processed_kernel: @@ -175,7 +150,17 @@ Index: linux-2.6.11-xendiffs/arch/ia64/kernel/entry.S adds r21=PT(PR)+16,r12 ;; -@@ -934,7 +1012,11 @@ GLOBAL_ENTRY(ia64_leave_kernel) +@@ -838,7 +885,9 @@ + ;; + ld8 r29=[r2],16 // load b7 + ld8 r30=[r3],16 // load ar.csd ++#ifndef XEN + (p6) br.cond.spnt .work_pending ++#endif + ;; + ld8 r31=[r2],16 // load ar.ssd + ld8.fill r8=[r3],16 +@@ -934,7 +983,11 @@ shr.u r18=r19,16 // get byte size of existing "dirty" partition ;; mov r16=ar.bsp // get existing backing store pointer @@ -187,15 +172,47 @@ Index: linux-2.6.11-xendiffs/arch/ia64/kernel/entry.S ;; ld4 r17=[r17] // r17 = cpu_data->phys_stacked_size_p8 (pKStk) br.cond.dpnt skip_rbs_switch -@@ -1323,6 +1405,7 @@ GLOBAL_ENTRY(unw_init_running) +@@ -1069,6 +1122,7 @@ + mov pr=r31,-1 // I0 + rfi // B + ++#ifndef XEN + /* + * On entry: + * r20 = ¤t->thread_info->pre_count (if CONFIG_PREEMPT) +@@ -1130,6 +1184,7 @@ + ld8 r8=[r2] + ld8 r10=[r3] + br.cond.sptk.many .work_processed_syscall // re-check ++#endif + + END(ia64_leave_kernel) + +@@ -1166,6 +1221,7 @@ br.ret.sptk.many rp - END(unw_init_running) + END(ia64_invoke_schedule_tail) + ++#ifndef XEN + /* + * Setup stack and call do_notify_resume_user(). Note that pSys and pNonSys need to + * be set up by the caller. We declare 8 input registers so the system call +@@ -1264,6 +1320,7 @@ + mov ar.unat=r9 + br.many b7 + END(sys_rt_sigreturn) ++#endif + + GLOBAL_ENTRY(ia64_prepare_handle_unaligned) + .prologue +@@ -1278,6 +1335,7 @@ + br.cond.sptk.many rp // goes to ia64_leave_kernel + END(ia64_prepare_handle_unaligned) +#ifndef XEN - .rodata - .align 8 - .globl sys_call_table -@@ -1585,3 +1668,4 @@ sys_call_table: + // + // unw_init_running(void (*callback)(info, arg), void *arg) + // +@@ -1585,3 +1643,4 @@ data8 sys_ni_syscall .org sys_call_table + 8*NR_syscalls // guard against failures to increase NR_syscalls diff --git a/xen/arch/ia64/patch/linux-2.6.11/hpsim_ssc.h b/xen/arch/ia64/patch/linux-2.6.11/hpsim_ssc.h deleted file mode 100644 index 421644b0f7..0000000000 --- a/xen/arch/ia64/patch/linux-2.6.11/hpsim_ssc.h +++ /dev/null @@ -1,31 +0,0 @@ - hpsim_ssc.h | 19 +++++++++++++++++++ - 1 files changed, 19 insertions(+) - -Index: linux-2.6.11/arch/ia64/hp/sim/hpsim_ssc.h -=================================================================== ---- linux-2.6.11.orig/arch/ia64/hp/sim/hpsim_ssc.h 2005-03-02 01:38:17.000000000 -0600 -+++ linux-2.6.11/arch/ia64/hp/sim/hpsim_ssc.h 2005-03-19 13:34:01.705520375 -0600 -@@ -33,4 +33,23 @@ - */ - extern long ia64_ssc (long arg0, long arg1, long arg2, long arg3, int nr); - -+#ifdef XEN -+/* Note: These are declared in linux/arch/ia64/hp/sim/simscsi.c but belong -+ * in linux/include/asm-ia64/hpsim_ssc.h, hence their addition here */ -+#define SSC_OPEN 50 -+#define SSC_CLOSE 51 -+#define SSC_READ 52 -+#define SSC_WRITE 53 -+#define SSC_GET_COMPLETION 54 -+#define SSC_WAIT_COMPLETION 55 -+ -+#define SSC_WRITE_ACCESS 2 -+#define SSC_READ_ACCESS 1 -+ -+struct ssc_disk_req { -+ unsigned long addr; -+ unsigned long len; -+}; -+#endif -+ - #endif /* _IA64_PLATFORM_HPSIM_SSC_H */ diff --git a/xen/arch/ia64/patch/linux-2.6.11/irq_ia64.c b/xen/arch/ia64/patch/linux-2.6.11/irq_ia64.c index f0983646c2..ba2c3bc1e4 100644 --- a/xen/arch/ia64/patch/linux-2.6.11/irq_ia64.c +++ b/xen/arch/ia64/patch/linux-2.6.11/irq_ia64.c @@ -1,111 +1,22 @@ - irq_ia64.c | 67 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - 1 files changed, 67 insertions(+) - -Index: linux-2.6.11-xendiffs/arch/ia64/kernel/irq_ia64.c -=================================================================== ---- linux-2.6.11-xendiffs.orig/arch/ia64/kernel/irq_ia64.c 2005-04-08 13:30:16.777174938 -0500 -+++ linux-2.6.11-xendiffs/arch/ia64/kernel/irq_ia64.c 2005-04-08 14:15:47.398616472 -0500 -@@ -17,18 +17,26 @@ - #include - #include - -+#ifndef XEN - #include -+#endif - #include - #include - #include - #include -+#ifndef XEN - #include -+#endif - #include -+#ifndef XEN - #include - #include /* for rand_initialize_irq() */ - #include -+#endif - #include -+#ifndef XEN - #include -+#endif - #include - #include - -@@ -104,6 +112,24 @@ void - ia64_handle_irq (ia64_vector vector, struct pt_regs *regs) - { +--- ../../linux-2.6.11/arch/ia64/kernel/irq_ia64.c 2005-03-02 00:38:07.000000000 -0700 ++++ arch/ia64/irq_ia64.c 2005-04-29 16:05:30.000000000 -0600 +@@ -106,6 +106,9 @@ unsigned long saved_tpr; -+#if 0 -+//FIXME: For debug only, can be removed -+ static char firstirq = 1; -+ static char firsttime[256]; -+ static char firstpend[256]; -+ if (firstirq) { -+ int i; -+ for (i=0;i<256;i++) firsttime[i] = 1; -+ for (i=0;i<256;i++) firstpend[i] = 1; -+ firstirq = 0; -+ } -+ if (firsttime[vector]) { -+ printf("**** (entry) First received int on vector=%d,itc=%lx\n", -+ (unsigned long) vector, ia64_get_itc()); -+ firsttime[vector] = 0; -+ } -+#endif -+ #if IRQ_DEBUG ++#ifdef XEN ++ xen_debug_irq(vector, regs); ++#endif { -@@ -148,6 +174,27 @@ ia64_handle_irq (ia64_vector vector, str + unsigned long bsp, sp; + +@@ -148,6 +151,9 @@ ia64_setreg(_IA64_REG_CR_TPR, vector); ia64_srlz_d(); +#ifdef XEN -+ if (vector != 0xef) { -+ extern void vcpu_pend_interrupt(void *, int); -+#if 0 -+ if (firsttime[vector]) { -+ printf("**** (iterate) First received int on vector=%d,itc=%lx\n", -+ (unsigned long) vector, ia64_get_itc()); -+ firsttime[vector] = 0; -+ } -+ if (firstpend[vector]) { -+ printf("**** First pended int on vector=%d,itc=%lx\n", -+ (unsigned long) vector,ia64_get_itc()); -+ firstpend[vector] = 0; -+ } -+#endif -+ //FIXME: TEMPORARY HACK!!!! -+ vcpu_pend_interrupt(dom0->exec_domain[0],vector); -+ domain_wake(dom0->exec_domain[0]); -+ } -+ else ++ if (!xen_do_IRQ(vector)) +#endif __do_IRQ(local_vector_to_irq(vector), regs); /* -@@ -276,3 +323,23 @@ ia64_send_ipi (int cpu, int vector, int - - writeq(ipi_data, ipi_addr); - } -+ -+/* From linux/kernel/softirq.c */ -+#ifdef __ARCH_IRQ_EXIT_IRQS_DISABLED -+# define invoke_softirq() __do_softirq() -+#else -+# define invoke_softirq() do_softirq() -+#endif -+ -+/* -+ * Exit an interrupt context. Process softirqs if needed and possible: -+ */ -+void irq_exit(void) -+{ -+ account_system_vtime(current); -+ sub_preempt_count(IRQ_EXIT_OFFSET); -+ if (!in_interrupt() && local_softirq_pending()) -+ invoke_softirq(); -+ preempt_enable_no_resched(); -+} -+/* end from linux/kernel/softirq.c */ diff --git a/xen/arch/ia64/patch/linux-2.6.11/ivt.S b/xen/arch/ia64/patch/linux-2.6.11/ivt.S deleted file mode 100644 index e8ee4e152e..0000000000 --- a/xen/arch/ia64/patch/linux-2.6.11/ivt.S +++ /dev/null @@ -1,533 +0,0 @@ - ivt.S | 254 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - 1 files changed, 254 insertions(+) - -Index: linux-2.6.11-xendiffs/arch/ia64/kernel/ivt.S -=================================================================== ---- linux-2.6.11-xendiffs.orig/arch/ia64/kernel/ivt.S 2005-04-07 10:29:00.565766924 -0500 -+++ linux-2.6.11-xendiffs/arch/ia64/kernel/ivt.S 2005-04-07 10:29:50.923594750 -0500 -@@ -1,3 +1,21 @@ -+ -+#ifdef XEN -+//#define CONFIG_DISABLE_VHPT // FIXME: change when VHPT is enabled?? -+// these are all hacked out for now as the entire IVT -+// will eventually be replaced... just want to use it -+// for startup code to handle TLB misses -+//#define ia64_leave_kernel 0 -+//#define ia64_ret_from_syscall 0 -+//#define ia64_handle_irq 0 -+//#define ia64_fault 0 -+#define ia64_illegal_op_fault 0 -+#define ia64_prepare_handle_unaligned 0 -+#define ia64_bad_break 0 -+#define ia64_trace_syscall 0 -+#define sys_call_table 0 -+#define sys_ni_syscall 0 -+#include -+#endif - /* - * arch/ia64/kernel/ivt.S - * -@@ -77,6 +95,13 @@ - mov r19=n;; /* prepare to save predicates */ \ - br.sptk.many dispatch_to_fault_handler - -+#ifdef XEN -+#define REFLECT(n) \ -+ mov r31=pr; \ -+ mov r19=n;; /* prepare to save predicates */ \ -+ br.sptk.many dispatch_reflection -+#endif -+ - .section .text.ivt,"ax" - - .align 32768 // align on 32KB boundary -@@ -214,6 +239,13 @@ END(vhpt_miss) - // 0x0400 Entry 1 (size 64 bundles) ITLB (21) - ENTRY(itlb_miss) - DBG_FAULT(1) -+#ifdef XEN -+ VHPT_CCHAIN_LOOKUP(itlb_miss,i) -+#ifdef VHPT_GLOBAL -+ br.cond.sptk page_fault -+ ;; -+#endif -+#endif - /* - * The ITLB handler accesses the L3 PTE via the virtually mapped linear - * page table. If a nested TLB miss occurs, we switch into physical -@@ -258,6 +290,13 @@ END(itlb_miss) - // 0x0800 Entry 2 (size 64 bundles) DTLB (9,48) - ENTRY(dtlb_miss) - DBG_FAULT(2) -+#ifdef XEN -+ VHPT_CCHAIN_LOOKUP(dtlb_miss,d) -+#ifdef VHPT_GLOBAL -+ br.cond.sptk page_fault -+ ;; -+#endif -+#endif - /* - * The DTLB handler accesses the L3 PTE via the virtually mapped linear - * page table. If a nested TLB miss occurs, we switch into physical -@@ -302,6 +341,13 @@ END(dtlb_miss) - // 0x0c00 Entry 3 (size 64 bundles) Alt ITLB (19) - ENTRY(alt_itlb_miss) - DBG_FAULT(3) -+#ifdef XEN -+//#ifdef VHPT_GLOBAL -+// VHPT_CCHAIN_LOOKUP(alt_itlb_miss,i) -+// br.cond.sptk page_fault -+// ;; -+//#endif -+#endif - mov r16=cr.ifa // get address that caused the TLB miss - movl r17=PAGE_KERNEL - mov r21=cr.ipsr -@@ -340,6 +386,13 @@ END(alt_itlb_miss) - // 0x1000 Entry 4 (size 64 bundles) Alt DTLB (7,46) - ENTRY(alt_dtlb_miss) - DBG_FAULT(4) -+#ifdef XEN -+//#ifdef VHPT_GLOBAL -+// VHPT_CCHAIN_LOOKUP(alt_dtlb_miss,d) -+// br.cond.sptk page_fault -+// ;; -+//#endif -+#endif - mov r16=cr.ifa // get address that caused the TLB miss - movl r17=PAGE_KERNEL - mov r20=cr.isr -@@ -369,6 +422,17 @@ ENTRY(alt_dtlb_miss) - cmp.ne p8,p0=r0,r23 - (p9) cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22 // check isr.code field - (p8) br.cond.spnt page_fault -+#ifdef XEN -+ ;; -+ // FIXME: inadequate test, this is where we test for Xen address -+ // note that 0xf000 (cached) and 0xd000 (uncached) addresses -+ // should be OK. (Though no I/O is done in Xen, EFI needs uncached -+ // addresses and some domain EFI calls are passed through) -+ tbit.nz p0,p8=r16,60 -+(p8) br.cond.spnt page_fault -+//(p8) br.cond.spnt 0 -+ ;; -+#endif - - dep r21=-1,r21,IA64_PSR_ED_BIT,1 - or r19=r19,r17 // insert PTE control bits into r19 -@@ -449,6 +513,9 @@ END(nested_dtlb_miss) - ///////////////////////////////////////////////////////////////////////////////////////// - // 0x1800 Entry 6 (size 64 bundles) Instruction Key Miss (24) - ENTRY(ikey_miss) -+#ifdef XEN -+ REFLECT(6) -+#endif - DBG_FAULT(6) - FAULT(6) - END(ikey_miss) -@@ -461,9 +528,16 @@ ENTRY(page_fault) - srlz.i - ;; - SAVE_MIN_WITH_COVER -+#ifdef XEN -+ alloc r15=ar.pfs,0,0,4,0 -+ mov out0=cr.ifa -+ mov out1=cr.isr -+ mov out3=cr.itir -+#else - alloc r15=ar.pfs,0,0,3,0 - mov out0=cr.ifa - mov out1=cr.isr -+#endif - adds r3=8,r2 // set up second base pointer - ;; - ssm psr.ic | PSR_DEFAULT_BITS -@@ -484,6 +558,9 @@ END(page_fault) - ///////////////////////////////////////////////////////////////////////////////////////// - // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51) - ENTRY(dkey_miss) -+#ifdef XEN -+ REFLECT(7) -+#endif - DBG_FAULT(7) - FAULT(7) - END(dkey_miss) -@@ -492,6 +569,9 @@ END(dkey_miss) - ///////////////////////////////////////////////////////////////////////////////////////// - // 0x2000 Entry 8 (size 64 bundles) Dirty-bit (54) - ENTRY(dirty_bit) -+#ifdef XEN -+ REFLECT(8) -+#endif - DBG_FAULT(8) - /* - * What we do here is to simply turn on the dirty bit in the PTE. We need to -@@ -554,6 +634,9 @@ END(dirty_bit) - ///////////////////////////////////////////////////////////////////////////////////////// - // 0x2400 Entry 9 (size 64 bundles) Instruction Access-bit (27) - ENTRY(iaccess_bit) -+#ifdef XEN -+ REFLECT(9) -+#endif - DBG_FAULT(9) - // Like Entry 8, except for instruction access - mov r16=cr.ifa // get the address that caused the fault -@@ -619,6 +702,9 @@ END(iaccess_bit) - ///////////////////////////////////////////////////////////////////////////////////////// - // 0x2800 Entry 10 (size 64 bundles) Data Access-bit (15,55) - ENTRY(daccess_bit) -+#ifdef XEN -+ REFLECT(10) -+#endif - DBG_FAULT(10) - // Like Entry 8, except for data access - mov r16=cr.ifa // get the address that caused the fault -@@ -687,6 +773,16 @@ ENTRY(break_fault) - * to prevent leaking bits from kernel to user level. - */ - DBG_FAULT(11) -+#ifdef XEN -+ mov r16=cr.isr -+ mov r17=cr.iim -+ mov r31=pr -+ ;; -+ cmp.eq p7,p0=r0,r17 // is this a psuedo-cover? -+ // FIXME: may also need to check slot==2? -+(p7) br.sptk.many dispatch_privop_fault -+ br.sptk.many dispatch_break_fault -+#endif - mov r16=IA64_KR(CURRENT) // r16 = current task; 12 cycle read lat. - mov r17=cr.iim - mov r18=__IA64_BREAK_SYSCALL -@@ -697,7 +793,9 @@ ENTRY(break_fault) - mov r27=ar.rsc - mov r26=ar.pfs - mov r28=cr.iip -+#ifndef XEN - mov r31=pr // prepare to save predicates -+#endif - mov r20=r1 - ;; - adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16 -@@ -797,6 +895,36 @@ END(interrupt) - DBG_FAULT(13) - FAULT(13) - -+#ifdef XEN -+ // There is no particular reason for this code to be here, other than that -+ // there happens to be space here that would go unused otherwise. If this -+ // fault ever gets "unreserved", simply moved the following code to a more -+ // suitable spot... -+ -+ENTRY(dispatch_break_fault) -+ SAVE_MIN_WITH_COVER -+ ;; -+ alloc r14=ar.pfs,0,0,4,0 // now it's safe (must be first in insn group!) -+ mov out0=cr.ifa -+ adds out1=16,sp -+ mov out2=cr.isr // FIXME: pity to make this slow access twice -+ mov out3=cr.iim // FIXME: pity to make this slow access twice -+ -+ ssm psr.ic | PSR_DEFAULT_BITS -+ ;; -+ srlz.i // guarantee that interruption collection is on -+ ;; -+(p15) ssm psr.i // restore psr.i -+ adds r3=8,r2 // set up second base pointer -+ ;; -+ SAVE_REST -+ movl r14=ia64_leave_kernel -+ ;; -+ mov rp=r14 -+ br.sptk.many ia64_prepare_handle_break -+END(dispatch_break_fault) -+#endif -+ - .org ia64_ivt+0x3800 - ///////////////////////////////////////////////////////////////////////////////////////// - // 0x3800 Entry 14 (size 64 bundles) Reserved -@@ -850,9 +978,11 @@ END(interrupt) - * - ar.fpsr: set to kernel settings - */ - GLOBAL_ENTRY(ia64_syscall_setup) -+#ifndef XEN - #if PT(B6) != 0 - # error This code assumes that b6 is the first field in pt_regs. - #endif -+#endif - st8 [r1]=r19 // save b6 - add r16=PT(CR_IPSR),r1 // initialize first base pointer - add r17=PT(R11),r1 // initialize second base pointer -@@ -992,6 +1122,37 @@ END(dispatch_illegal_op_fault) - DBG_FAULT(16) - FAULT(16) - -+#ifdef XEN -+ // There is no particular reason for this code to be here, other than that -+ // there happens to be space here that would go unused otherwise. If this -+ // fault ever gets "unreserved", simply moved the following code to a more -+ // suitable spot... -+ -+ENTRY(dispatch_privop_fault) -+ SAVE_MIN_WITH_COVER -+ ;; -+ alloc r14=ar.pfs,0,0,4,0 // now it's safe (must be first in insn group!) -+ mov out0=cr.ifa -+ adds out1=16,sp -+ mov out2=cr.isr // FIXME: pity to make this slow access twice -+ mov out3=cr.itir -+ -+ ssm psr.ic | PSR_DEFAULT_BITS -+ ;; -+ srlz.i // guarantee that interruption collection is on -+ ;; -+(p15) ssm psr.i // restore psr.i -+ adds r3=8,r2 // set up second base pointer -+ ;; -+ SAVE_REST -+ movl r14=ia64_leave_kernel -+ ;; -+ mov rp=r14 -+ br.sptk.many ia64_prepare_handle_privop -+END(dispatch_privop_fault) -+#endif -+ -+ - .org ia64_ivt+0x4400 - ///////////////////////////////////////////////////////////////////////////////////////// - // 0x4400 Entry 17 (size 64 bundles) Reserved -@@ -1108,6 +1269,9 @@ END(dispatch_to_fault_handler) - ///////////////////////////////////////////////////////////////////////////////////////// - // 0x5000 Entry 20 (size 16 bundles) Page Not Present (10,22,49) - ENTRY(page_not_present) -+#ifdef XEN -+ REFLECT(20) -+#endif - DBG_FAULT(20) - mov r16=cr.ifa - rsm psr.dt -@@ -1128,6 +1292,9 @@ END(page_not_present) - ///////////////////////////////////////////////////////////////////////////////////////// - // 0x5100 Entry 21 (size 16 bundles) Key Permission (13,25,52) - ENTRY(key_permission) -+#ifdef XEN -+ REFLECT(21) -+#endif - DBG_FAULT(21) - mov r16=cr.ifa - rsm psr.dt -@@ -1141,6 +1308,9 @@ END(key_permission) - ///////////////////////////////////////////////////////////////////////////////////////// - // 0x5200 Entry 22 (size 16 bundles) Instruction Access Rights (26) - ENTRY(iaccess_rights) -+#ifdef XEN -+ REFLECT(22) -+#endif - DBG_FAULT(22) - mov r16=cr.ifa - rsm psr.dt -@@ -1154,6 +1324,9 @@ END(iaccess_rights) - ///////////////////////////////////////////////////////////////////////////////////////// - // 0x5300 Entry 23 (size 16 bundles) Data Access Rights (14,53) - ENTRY(daccess_rights) -+#ifdef XEN -+ REFLECT(23) -+#endif - DBG_FAULT(23) - mov r16=cr.ifa - rsm psr.dt -@@ -1171,8 +1344,13 @@ ENTRY(general_exception) - mov r16=cr.isr - mov r31=pr - ;; -+#ifdef XEN -+ cmp4.ge p6,p0=0x20,r16 -+(p6) br.sptk.many dispatch_privop_fault -+#else - cmp4.eq p6,p0=0,r16 - (p6) br.sptk.many dispatch_illegal_op_fault -+#endif - ;; - mov r19=24 // fault number - br.sptk.many dispatch_to_fault_handler -@@ -1182,6 +1360,9 @@ END(general_exception) - ///////////////////////////////////////////////////////////////////////////////////////// - // 0x5500 Entry 25 (size 16 bundles) Disabled FP-Register (35) - ENTRY(disabled_fp_reg) -+#ifdef XEN -+ REFLECT(25) -+#endif - DBG_FAULT(25) - rsm psr.dfh // ensure we can access fph - ;; -@@ -1195,6 +1376,9 @@ END(disabled_fp_reg) - ///////////////////////////////////////////////////////////////////////////////////////// - // 0x5600 Entry 26 (size 16 bundles) Nat Consumption (11,23,37,50) - ENTRY(nat_consumption) -+#ifdef XEN -+ REFLECT(26) -+#endif - DBG_FAULT(26) - FAULT(26) - END(nat_consumption) -@@ -1203,6 +1387,10 @@ END(nat_consumption) - ///////////////////////////////////////////////////////////////////////////////////////// - // 0x5700 Entry 27 (size 16 bundles) Speculation (40) - ENTRY(speculation_vector) -+#ifdef XEN -+ // this probably need not reflect... -+ REFLECT(27) -+#endif - DBG_FAULT(27) - /* - * A [f]chk.[as] instruction needs to take the branch to the recovery code but -@@ -1246,6 +1434,9 @@ END(speculation_vector) - ///////////////////////////////////////////////////////////////////////////////////////// - // 0x5900 Entry 29 (size 16 bundles) Debug (16,28,56) - ENTRY(debug_vector) -+#ifdef XEN -+ REFLECT(29) -+#endif - DBG_FAULT(29) - FAULT(29) - END(debug_vector) -@@ -1254,6 +1445,9 @@ END(debug_vector) - ///////////////////////////////////////////////////////////////////////////////////////// - // 0x5a00 Entry 30 (size 16 bundles) Unaligned Reference (57) - ENTRY(unaligned_access) -+#ifdef XEN -+ REFLECT(30) -+#endif - DBG_FAULT(30) - mov r16=cr.ipsr - mov r31=pr // prepare to save predicates -@@ -1265,6 +1459,9 @@ END(unaligned_access) - ///////////////////////////////////////////////////////////////////////////////////////// - // 0x5b00 Entry 31 (size 16 bundles) Unsupported Data Reference (57) - ENTRY(unsupported_data_reference) -+#ifdef XEN -+ REFLECT(31) -+#endif - DBG_FAULT(31) - FAULT(31) - END(unsupported_data_reference) -@@ -1273,6 +1470,9 @@ END(unsupported_data_reference) - ///////////////////////////////////////////////////////////////////////////////////////// - // 0x5c00 Entry 32 (size 16 bundles) Floating-Point Fault (64) - ENTRY(floating_point_fault) -+#ifdef XEN -+ REFLECT(32) -+#endif - DBG_FAULT(32) - FAULT(32) - END(floating_point_fault) -@@ -1281,6 +1481,9 @@ END(floating_point_fault) - ///////////////////////////////////////////////////////////////////////////////////////// - // 0x5d00 Entry 33 (size 16 bundles) Floating Point Trap (66) - ENTRY(floating_point_trap) -+#ifdef XEN -+ REFLECT(33) -+#endif - DBG_FAULT(33) - FAULT(33) - END(floating_point_trap) -@@ -1289,6 +1492,9 @@ END(floating_point_trap) - ///////////////////////////////////////////////////////////////////////////////////////// - // 0x5e00 Entry 34 (size 16 bundles) Lower Privilege Transfer Trap (66) - ENTRY(lower_privilege_trap) -+#ifdef XEN -+ REFLECT(34) -+#endif - DBG_FAULT(34) - FAULT(34) - END(lower_privilege_trap) -@@ -1297,6 +1503,9 @@ END(lower_privilege_trap) - ///////////////////////////////////////////////////////////////////////////////////////// - // 0x5f00 Entry 35 (size 16 bundles) Taken Branch Trap (68) - ENTRY(taken_branch_trap) -+#ifdef XEN -+ REFLECT(35) -+#endif - DBG_FAULT(35) - FAULT(35) - END(taken_branch_trap) -@@ -1305,6 +1514,9 @@ END(taken_branch_trap) - ///////////////////////////////////////////////////////////////////////////////////////// - // 0x6000 Entry 36 (size 16 bundles) Single Step Trap (69) - ENTRY(single_step_trap) -+#ifdef XEN -+ REFLECT(36) -+#endif - DBG_FAULT(36) - FAULT(36) - END(single_step_trap) -@@ -1361,6 +1573,9 @@ END(single_step_trap) - ///////////////////////////////////////////////////////////////////////////////////////// - // 0x6900 Entry 45 (size 16 bundles) IA-32 Exeception (17,18,29,41,42,43,44,58,60,61,62,72,73,75,76,77) - ENTRY(ia32_exception) -+#ifdef XEN -+ REFLECT(45) -+#endif - DBG_FAULT(45) - FAULT(45) - END(ia32_exception) -@@ -1369,6 +1584,9 @@ END(ia32_exception) - ///////////////////////////////////////////////////////////////////////////////////////// - // 0x6a00 Entry 46 (size 16 bundles) IA-32 Intercept (30,31,59,70,71) - ENTRY(ia32_intercept) -+#ifdef XEN -+ REFLECT(46) -+#endif - DBG_FAULT(46) - #ifdef CONFIG_IA32_SUPPORT - mov r31=pr -@@ -1399,6 +1617,9 @@ END(ia32_intercept) - ///////////////////////////////////////////////////////////////////////////////////////// - // 0x6b00 Entry 47 (size 16 bundles) IA-32 Interrupt (74) - ENTRY(ia32_interrupt) -+#ifdef XEN -+ REFLECT(47) -+#endif - DBG_FAULT(47) - #ifdef CONFIG_IA32_SUPPORT - mov r31=pr -@@ -1528,6 +1749,39 @@ END(ia32_interrupt) - DBG_FAULT(67) - FAULT(67) - -+#ifdef XEN -+ .org ia64_ivt+0x8000 -+ENTRY(dispatch_reflection) -+ /* -+ * Input: -+ * psr.ic: off -+ * r19: intr type (offset into ivt, see ia64_int.h) -+ * r31: contains saved predicates (pr) -+ */ -+ SAVE_MIN_WITH_COVER_R19 -+ alloc r14=ar.pfs,0,0,5,0 -+ mov out4=r15 -+ mov out0=cr.ifa -+ adds out1=16,sp -+ mov out2=cr.isr -+ mov out3=cr.iim -+// mov out3=cr.itir -+ -+ ssm psr.ic | PSR_DEFAULT_BITS -+ ;; -+ srlz.i // guarantee that interruption collection is on -+ ;; -+(p15) ssm psr.i // restore psr.i -+ adds r3=8,r2 // set up second base pointer -+ ;; -+ SAVE_REST -+ movl r14=ia64_leave_kernel -+ ;; -+ mov rp=r14 -+ br.sptk.many ia64_prepare_handle_reflection -+END(dispatch_reflection) -+#endif -+ - #ifdef CONFIG_IA32_SUPPORT - - /* diff --git a/xen/arch/ia64/patch/linux-2.6.11/lds.S b/xen/arch/ia64/patch/linux-2.6.11/lds.S deleted file mode 100644 index a2860c40d3..0000000000 --- a/xen/arch/ia64/patch/linux-2.6.11/lds.S +++ /dev/null @@ -1,22 +0,0 @@ - vmlinux.lds.S | 2 ++ - 1 files changed, 2 insertions(+) - -Index: linux-2.6.11/arch/ia64/kernel/vmlinux.lds.S -=================================================================== ---- linux-2.6.11.orig/arch/ia64/kernel/vmlinux.lds.S 2005-03-02 01:38:25.000000000 -0600 -+++ linux-2.6.11/arch/ia64/kernel/vmlinux.lds.S 2005-03-19 13:44:28.746368232 -0600 -@@ -11,12 +11,14 @@ - OUTPUT_FORMAT("elf64-ia64-little") - OUTPUT_ARCH(ia64) - ENTRY(phys_start) -+#ifndef XEN - jiffies = jiffies_64; - PHDRS { - code PT_LOAD; - percpu PT_LOAD; - data PT_LOAD; - } -+#endif - SECTIONS - { - /* Sections to be discarded */ diff --git a/xen/arch/ia64/tools/mkbuildtree b/xen/arch/ia64/tools/mkbuildtree index 66b7b4fa0e..998ce2b832 100644 --- a/xen/arch/ia64/tools/mkbuildtree +++ b/xen/arch/ia64/tools/mkbuildtree @@ -85,7 +85,7 @@ cp_patch arch/ia64/kernel/entry.S arch/ia64/entry.S entry.S cp_patch arch/ia64/kernel/head.S arch/ia64/head.S head.S #cp_patch arch/ia64/kernel/init_task.c arch/ia64/init_task.c init_task.c cp_patch arch/ia64/kernel/irq_ia64.c arch/ia64/irq_ia64.c irq_ia64.c -cp_patch arch/ia64/kernel/ivt.S arch/ia64/ivt.S ivt.S +#cp_patch arch/ia64/kernel/ivt.S arch/ia64/ivt.S ivt.S #cp_patch arch/ia64/kernel/minstate.h arch/ia64/minstate.h minstate.h cp_patch arch/ia64/kernel/setup.c arch/ia64/setup.c setup.c cp_patch arch/ia64/kernel/time.c arch/ia64/time.c time.c @@ -317,6 +317,11 @@ null include/asm-ia64/linux/profile.h null include/asm-ia64/linux/seqlock.h null include/asm-ia64/linux/smp_lock.h null include/asm-ia64/linux/tty.h +null include/asm-ia64/linux/jiffies.h +null include/asm-ia64/linux/kernel_stat.h +null include/asm-ia64/linux/ptrace.h +null include/asm-ia64/linux/random.h +null include/asm-ia64/linux/signal.h softlink include/linux/byteorder/generic.h include/asm-ia64/linux/byteorder/generic.h softlink include/linux/byteorder/little_endian.h include/asm-ia64/linux/byteorder/little_endian.h diff --git a/xen/arch/ia64/xenirq.c b/xen/arch/ia64/xenirq.c new file mode 100644 index 0000000000..8809122751 --- /dev/null +++ b/xen/arch/ia64/xenirq.c @@ -0,0 +1,77 @@ +/* + * Xen irq routines + * + * Copyright (C) 2005 Hewlett-Packard Co. + * Dan Magenheimer (dan.magenheimer@hp.com) + * + */ + +#include +#include + + +void +xen_debug_irq(ia64_vector vector, struct pt_regs *regs) +{ +//FIXME: For debug only, can be removed + static char firstirq = 1; + static char firsttime[256]; + static char firstpend[256]; + if (firstirq) { + int i; + for (i=0;i<256;i++) firsttime[i] = 1; + for (i=0;i<256;i++) firstpend[i] = 1; + firstirq = 0; + } + if (firsttime[vector]) { + printf("**** (entry) First received int on vector=%d,itc=%lx\n", + (unsigned long) vector, ia64_get_itc()); + firsttime[vector] = 0; + } +} + + +int +xen_do_IRQ(ia64_vector vector) +{ + if (vector != 0xef) { + extern void vcpu_pend_interrupt(void *, int); +#if 0 + if (firsttime[vector]) { + printf("**** (iterate) First received int on vector=%d,itc=%lx\n", + (unsigned long) vector, ia64_get_itc()); + firsttime[vector] = 0; + } + if (firstpend[vector]) { + printf("**** First pended int on vector=%d,itc=%lx\n", + (unsigned long) vector,ia64_get_itc()); + firstpend[vector] = 0; + } +#endif + //FIXME: TEMPORARY HACK!!!! + vcpu_pend_interrupt(dom0->exec_domain[0],vector); + domain_wake(dom0->exec_domain[0]); + return(1); + } + return(0); +} + +/* From linux/kernel/softirq.c */ +#ifdef __ARCH_IRQ_EXIT_IRQS_DISABLED +# define invoke_softirq() __do_softirq() +#else +# define invoke_softirq() do_softirq() +#endif + +/* + * Exit an interrupt context. Process softirqs if needed and possible: + */ +void irq_exit(void) +{ + //account_system_vtime(current); + //sub_preempt_count(IRQ_EXIT_OFFSET); + if (!in_interrupt() && local_softirq_pending()) + invoke_softirq(); + //preempt_enable_no_resched(); +} +/* end from linux/kernel/softirq.c */ -- 2.30.2